Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Real Time Clock interface for StrongARM SA1x00 and XScale PXA2xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2000 Nils Faerber
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Based on rtc.c by Paul Gortmaker
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Original Driver by Nils Faerber <nils@kernelconcepts.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Modifications from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *   CIH <cih@coventive.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *   Nicolas Pitre <nico@fluxnic.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *   Andrew Christian <andrew.christian@hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * Converted to the RTC subsystem and Driver Model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *   by Richard Purdie <rpurdie@rpsys.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define RTSR_HZE		BIT(3)	/* HZ interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define RTSR_ALE		BIT(2)	/* RTC alarm interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define RTSR_HZ			BIT(1)	/* HZ rising-edge detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define RTSR_AL			BIT(0)	/* RTC alarm detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include "rtc-sa1100.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define RTC_DEF_DIVIDER		(32768 - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define RTC_DEF_TRIM		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define RTC_FREQ		1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static irqreturn_t sa1100_rtc_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct sa1100_rtc *info = dev_get_drvdata(dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct rtc_device *rtc = info->rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	unsigned int rtsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	unsigned long events = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	spin_lock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	rtsr = readl_relaxed(info->rtsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	/* clear interrupt sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	writel_relaxed(0, info->rtsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	/* Fix for a nasty initialization problem the in SA11xx RTSR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	 * See also the comments in sa1100_rtc_probe(). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	if (rtsr & (RTSR_ALE | RTSR_HZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		/* This is the original code, before there was the if test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		 * above. This code does not clear interrupts that were not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		 * enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		writel_relaxed((RTSR_AL | RTSR_HZ) & (rtsr >> 2), info->rtsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		/* For some reason, it is possible to enter this routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		 * without interruptions enabled, it has been tested with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		 * several units (Bug in SA11xx chip?).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		 * This situation leads to an infinite "loop" of interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		 * routine calling and as a result the processor seems to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		 * lock on its first call to open(). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	/* clear alarm interrupt if it has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	if (rtsr & RTSR_AL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		rtsr &= ~RTSR_ALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	writel_relaxed(rtsr & (RTSR_ALE | RTSR_HZE), info->rtsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	/* update irq data & counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	if (rtsr & RTSR_AL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		events |= RTC_AF | RTC_IRQF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (rtsr & RTSR_HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		events |= RTC_UF | RTC_IRQF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	rtc_update_irq(rtc, 1, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	spin_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static int sa1100_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u32 rtsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct sa1100_rtc *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	spin_lock_irq(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	rtsr = readl_relaxed(info->rtsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		rtsr |= RTSR_ALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		rtsr &= ~RTSR_ALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	writel_relaxed(rtsr, info->rtsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	spin_unlock_irq(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int sa1100_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct sa1100_rtc *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	rtc_time64_to_tm(readl_relaxed(info->rcnr), tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int sa1100_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	struct sa1100_rtc *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	writel_relaxed(rtc_tm_to_time64(tm), info->rcnr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int sa1100_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	u32	rtsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	struct sa1100_rtc *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	rtsr = readl_relaxed(info->rtsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	alrm->enabled = (rtsr & RTSR_ALE) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	alrm->pending = (rtsr & RTSR_AL) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int sa1100_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct sa1100_rtc *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	spin_lock_irq(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	writel_relaxed(readl_relaxed(info->rtsr) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		(RTSR_HZE | RTSR_ALE | RTSR_AL), info->rtsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	writel_relaxed(rtc_tm_to_time64(&alrm->time), info->rtar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (alrm->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		writel_relaxed(readl_relaxed(info->rtsr) | RTSR_ALE, info->rtsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		writel_relaxed(readl_relaxed(info->rtsr) & ~RTSR_ALE, info->rtsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	spin_unlock_irq(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int sa1100_rtc_proc(struct device *dev, struct seq_file *seq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	struct sa1100_rtc *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	seq_printf(seq, "trim/divider\t\t: 0x%08x\n", readl_relaxed(info->rttr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	seq_printf(seq, "RTSR\t\t\t: 0x%08x\n", readl_relaxed(info->rtsr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const struct rtc_class_ops sa1100_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.read_time = sa1100_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.set_time = sa1100_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.read_alarm = sa1100_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.set_alarm = sa1100_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.proc = sa1100_rtc_proc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.alarm_irq_enable = sa1100_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int sa1100_rtc_init(struct platform_device *pdev, struct sa1100_rtc *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	spin_lock_init(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	info->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (IS_ERR(info->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		dev_err(&pdev->dev, "failed to find rtc clock source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return PTR_ERR(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	ret = clk_prepare_enable(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	 * According to the manual we should be able to let RTTR be zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	 * and then a default diviser for a 32.768KHz clock is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	 * Apparently this doesn't work, at least for my SA1110 rev 5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 * If the clock divider is uninitialized then reset it to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 * default value to get the 1Hz clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (readl_relaxed(info->rttr) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		writel_relaxed(RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16), info->rttr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		dev_warn(&pdev->dev, "warning: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			"initializing default clock divider/trim value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		/* The current RTC value probably doesn't make sense either */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		writel_relaxed(0, info->rcnr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	info->rtc->ops = &sa1100_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	info->rtc->max_user_freq = RTC_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	info->rtc->range_max = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	ret = rtc_register_device(info->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		clk_disable_unprepare(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	/* Fix for a nasty initialization problem the in SA11xx RTSR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	 * See also the comments in sa1100_rtc_interrupt().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	 * Sometimes bit 1 of the RTSR (RTSR_HZ) will wake up 1, which means an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	 * interrupt pending, even though interrupts were never enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	 * In this case, this bit it must be reset before enabling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	 * interruptions to avoid a nonexistent interrupt to occur.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	 * In principle, the same problem would apply to bit 0, although it has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	 * never been observed to happen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	 * This issue is addressed both here and in sa1100_rtc_interrupt().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	 * If the issue is not addressed here, in the times when the processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	 * wakes up with the bit set there will be one spurious interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	 * The issue is also dealt with in sa1100_rtc_interrupt() to be on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	 * safe side, once the condition that lead to this strange
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	 * initialization is unknown and could in principle happen during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	 * normal processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	 * Notice that clearing bit 1 and 0 is accomplished by writting ONES to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 * the corresponding bits in RTSR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	writel_relaxed(RTSR_AL | RTSR_HZ, info->rtsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) EXPORT_SYMBOL_GPL(sa1100_rtc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int sa1100_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	struct sa1100_rtc *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	int irq_1hz, irq_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	irq_1hz = platform_get_irq_byname(pdev, "rtc 1Hz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	irq_alarm = platform_get_irq_byname(pdev, "rtc alarm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	if (irq_1hz < 0 || irq_alarm < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	info = devm_kzalloc(&pdev->dev, sizeof(struct sa1100_rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	info->irq_1hz = irq_1hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	info->irq_alarm = irq_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	info->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	if (IS_ERR(info->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		return PTR_ERR(info->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	ret = devm_request_irq(&pdev->dev, irq_1hz, sa1100_rtc_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			       "rtc 1Hz", &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		dev_err(&pdev->dev, "IRQ %d already in use.\n", irq_1hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	ret = devm_request_irq(&pdev->dev, irq_alarm, sa1100_rtc_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 			       "rtc Alrm", &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		dev_err(&pdev->dev, "IRQ %d already in use.\n", irq_alarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (IS_ENABLED(CONFIG_ARCH_SA1100) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	    of_device_is_compatible(pdev->dev.of_node, "mrvl,sa1100-rtc")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		info->rcnr = base + 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		info->rtsr = base + 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		info->rtar = base + 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		info->rttr = base + 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		info->rcnr = base + 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		info->rtsr = base + 0x8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		info->rtar = base + 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		info->rttr = base + 0xc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	platform_set_drvdata(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	return sa1100_rtc_init(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int sa1100_rtc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	struct sa1100_rtc *info = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	if (info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		spin_lock_irq(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		writel_relaxed(0, info->rtsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		spin_unlock_irq(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		clk_disable_unprepare(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int sa1100_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	struct sa1100_rtc *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		enable_irq_wake(info->irq_alarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static int sa1100_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	struct sa1100_rtc *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		disable_irq_wake(info->irq_alarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static SIMPLE_DEV_PM_OPS(sa1100_rtc_pm_ops, sa1100_rtc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			sa1100_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const struct of_device_id sa1100_rtc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	{ .compatible = "mrvl,sa1100-rtc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	{ .compatible = "mrvl,mmp-rtc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MODULE_DEVICE_TABLE(of, sa1100_rtc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static struct platform_driver sa1100_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	.probe		= sa1100_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	.remove		= sa1100_rtc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		.name	= "sa1100-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		.pm	= &sa1100_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		.of_match_table = of_match_ptr(sa1100_rtc_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) module_platform_driver(sa1100_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) MODULE_DESCRIPTION("SA11x0/PXA2xx Realtime Clock Driver (RTC)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MODULE_ALIAS("platform:sa1100-rtc");