^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2013-2014 Samsung Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Copyright (C) 2013 Google, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/samsung/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mfd/samsung/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mfd/samsung/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mfd/samsung/s2mps14.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Maximum number of retries for checking changes in UDR field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * of S5M_RTC_UDR_CON register (to limit possible endless loop).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * After writing to RTC registers (setting time or alarm) read the UDR field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * in S5M_RTC_UDR_CON register. UDR is auto-cleared when data have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * been transferred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define UDR_READ_RETRY_CNT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) RTC_SEC = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) RTC_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) RTC_HOUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) RTC_WEEKDAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) RTC_DATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) RTC_MONTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) RTC_YEAR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) RTC_YEAR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Make sure this is always the last enum name. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) RTC_MAX_NUM_TIME_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Registers used by the driver which are different between chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Operations like read time and write alarm/time require updating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * specific fields in UDR register. These fields usually are auto-cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * (with some exceptions).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Table of operations per device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Device | Write time | Read time | Write alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * =================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * S5M8767 | UDR + TIME | | UDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * S2MPS11/14 | WUDR | RUDR | WUDR + RUDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * S2MPS13 | WUDR | RUDR | WUDR + AUDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * S2MPS15 | WUDR | RUDR | AUDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct s5m_rtc_reg_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Number of registers used for setting time/alarm0/alarm1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int regs_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* First register for time, seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* RTC control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned int ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* First register for alarm 0, seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned int alarm0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* First register for alarm 1, seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned int alarm1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Register for update flag (UDR). Typically setting UDR field to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * will enable update of time or alarm register. Then it will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * auto-cleared after successful update.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned int udr_update;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Auto-cleared mask in UDR field for writing time and alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int autoclear_udr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Masks in UDR field for time and alarm operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * The read time mask can be 0. Rest should not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int read_time_udr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned int write_time_udr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int write_alarm_udr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Register map for S5M8763 and S5M8767 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const struct s5m_rtc_reg_config s5m_rtc_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .regs_count = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .time = S5M_RTC_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .ctrl = S5M_ALARM1_CONF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .alarm0 = S5M_ALARM0_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .alarm1 = S5M_ALARM1_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .udr_update = S5M_RTC_UDR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .autoclear_udr_mask = S5M_RTC_UDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .read_time_udr_mask = 0, /* Not needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .write_time_udr_mask = S5M_RTC_UDR_MASK | S5M_RTC_TIME_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .write_alarm_udr_mask = S5M_RTC_UDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Register map for S2MPS13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const struct s5m_rtc_reg_config s2mps13_rtc_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .regs_count = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .time = S2MPS_RTC_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .ctrl = S2MPS_RTC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .alarm0 = S2MPS_ALARM0_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .alarm1 = S2MPS_ALARM1_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .udr_update = S2MPS_RTC_UDR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .read_time_udr_mask = S2MPS_RTC_RUDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .write_time_udr_mask = S2MPS_RTC_WUDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .write_alarm_udr_mask = S2MPS_RTC_WUDR_MASK | S2MPS13_RTC_AUDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Register map for S2MPS11/14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const struct s5m_rtc_reg_config s2mps14_rtc_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .regs_count = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .time = S2MPS_RTC_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .ctrl = S2MPS_RTC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .alarm0 = S2MPS_ALARM0_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .alarm1 = S2MPS_ALARM1_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .udr_update = S2MPS_RTC_UDR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .read_time_udr_mask = S2MPS_RTC_RUDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .write_time_udr_mask = S2MPS_RTC_WUDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .write_alarm_udr_mask = S2MPS_RTC_WUDR_MASK | S2MPS_RTC_RUDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * Register map for S2MPS15 - in comparison to S2MPS14 the WUDR and AUDR bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * are swapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct s5m_rtc_reg_config s2mps15_rtc_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .regs_count = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .time = S2MPS_RTC_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .ctrl = S2MPS_RTC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .alarm0 = S2MPS_ALARM0_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .alarm1 = S2MPS_ALARM1_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .udr_update = S2MPS_RTC_UDR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .autoclear_udr_mask = S2MPS_RTC_WUDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .read_time_udr_mask = S2MPS_RTC_RUDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .write_time_udr_mask = S2MPS15_RTC_WUDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .write_alarm_udr_mask = S2MPS15_RTC_AUDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct s5m_rtc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct i2c_client *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct sec_pmic_dev *s5m87xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct rtc_device *rtc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) enum sec_device_type device_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int rtc_24hr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) const struct s5m_rtc_reg_config *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const struct regmap_config s5m_rtc_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .max_register = S5M_RTC_REG_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct regmap_config s2mps14_rtc_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .max_register = S2MPS_RTC_REG_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void s5m8767_data_to_tm(u8 *data, struct rtc_time *tm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int rtc_24hr_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) tm->tm_sec = data[RTC_SEC] & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) tm->tm_min = data[RTC_MIN] & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (rtc_24hr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) tm->tm_hour = data[RTC_HOUR] & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) tm->tm_hour = data[RTC_HOUR] & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (data[RTC_HOUR] & HOUR_PM_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) tm->tm_hour += 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) tm->tm_wday = ffs(data[RTC_WEEKDAY] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) tm->tm_mday = data[RTC_DATE] & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) tm->tm_year = (data[RTC_YEAR1] & 0x7f) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) tm->tm_yday = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) tm->tm_isdst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int s5m8767_tm_to_data(struct rtc_time *tm, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) data[RTC_SEC] = tm->tm_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) data[RTC_MIN] = tm->tm_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (tm->tm_hour >= 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) data[RTC_HOUR] = tm->tm_hour | HOUR_PM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) data[RTC_HOUR] = tm->tm_hour & ~HOUR_PM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) data[RTC_WEEKDAY] = 1 << tm->tm_wday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) data[RTC_DATE] = tm->tm_mday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) data[RTC_MONTH] = tm->tm_mon + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) data[RTC_YEAR1] = tm->tm_year > 100 ? (tm->tm_year - 100) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (tm->tm_year < 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) pr_err("RTC cannot handle the year %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 1900 + tm->tm_year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * Read RTC_UDR_CON register and wait till UDR field is cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * This indicates that time/alarm update ended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int s5m8767_wait_for_udr_update(struct s5m_rtc_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int ret, retry = UDR_READ_RETRY_CNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ret = regmap_read(info->regmap, info->regs->udr_update, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) } while (--retry && (data & info->regs->autoclear_udr_mask) && !ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!retry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_err(info->dev, "waiting for UDR update, reached max number of retries\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int s5m_check_peding_alarm_interrupt(struct s5m_rtc_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) switch (info->device_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case S5M8767X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case S5M8763X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ret = regmap_read(info->regmap, S5M_RTC_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) val &= S5M_ALARM0_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case S2MPS15X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case S2MPS14X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case S2MPS13X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = regmap_read(info->s5m87xx->regmap_pmic, S2MPS14_REG_ST2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) val &= S2MPS_ALARM0_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) alarm->pending = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) alarm->pending = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int s5m8767_rtc_set_time_reg(struct s5m_rtc_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ret = regmap_read(info->regmap, info->regs->udr_update, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev_err(info->dev, "failed to read update reg(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) data |= info->regs->write_time_udr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ret = regmap_write(info->regmap, info->regs->udr_update, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dev_err(info->dev, "failed to write update reg(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = s5m8767_wait_for_udr_update(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int s5m8767_rtc_set_alarm_reg(struct s5m_rtc_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ret = regmap_read(info->regmap, info->regs->udr_update, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dev_err(info->dev, "%s: fail to read update reg(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) data |= info->regs->write_alarm_udr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) switch (info->device_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) case S5M8763X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case S5M8767X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) data &= ~S5M_RTC_TIME_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case S2MPS15X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case S2MPS14X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) case S2MPS13X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* No exceptions needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ret = regmap_write(info->regmap, info->regs->udr_update, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dev_err(info->dev, "%s: fail to write update reg(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret = s5m8767_wait_for_udr_update(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* On S2MPS13 the AUDR is not auto-cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (info->device_type == S2MPS13X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) regmap_update_bits(info->regmap, info->regs->udr_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) S2MPS13_RTC_AUDR_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static void s5m8763_data_to_tm(u8 *data, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) tm->tm_sec = bcd2bin(data[RTC_SEC]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) tm->tm_min = bcd2bin(data[RTC_MIN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (data[RTC_HOUR] & HOUR_12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) tm->tm_hour = bcd2bin(data[RTC_HOUR] & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (data[RTC_HOUR] & HOUR_PM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) tm->tm_hour += 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) tm->tm_hour = bcd2bin(data[RTC_HOUR] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) tm->tm_wday = data[RTC_WEEKDAY] & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) tm->tm_mday = bcd2bin(data[RTC_DATE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) tm->tm_mon = bcd2bin(data[RTC_MONTH]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) tm->tm_year = bcd2bin(data[RTC_YEAR1]) + bcd2bin(data[RTC_YEAR2]) * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) tm->tm_year -= 1900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void s5m8763_tm_to_data(struct rtc_time *tm, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) data[RTC_SEC] = bin2bcd(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) data[RTC_MIN] = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) data[RTC_HOUR] = bin2bcd(tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) data[RTC_WEEKDAY] = tm->tm_wday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) data[RTC_DATE] = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) data[RTC_MONTH] = bin2bcd(tm->tm_mon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) data[RTC_YEAR1] = bin2bcd(tm->tm_year % 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) data[RTC_YEAR2] = bin2bcd((tm->tm_year + 1900) / 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int s5m_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct s5m_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u8 data[RTC_MAX_NUM_TIME_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (info->regs->read_time_udr_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ret = regmap_update_bits(info->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) info->regs->udr_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) info->regs->read_time_udr_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) info->regs->read_time_udr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "Failed to prepare registers for time reading: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ret = regmap_bulk_read(info->regmap, info->regs->time, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) info->regs->regs_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) switch (info->device_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) case S5M8763X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) s5m8763_data_to_tm(data, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case S5M8767X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case S2MPS15X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case S2MPS14X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) case S2MPS13X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) s5m8767_data_to_tm(data, tm, info->rtc_24hr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_dbg(dev, "%s: %ptR(%d)\n", __func__, tm, tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int s5m_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct s5m_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u8 data[RTC_MAX_NUM_TIME_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) switch (info->device_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) case S5M8763X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) s5m8763_tm_to_data(tm, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) case S5M8767X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) case S2MPS15X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case S2MPS14X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case S2MPS13X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ret = s5m8767_tm_to_data(tm, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dev_dbg(dev, "%s: %ptR(%d)\n", __func__, tm, tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ret = regmap_raw_write(info->regmap, info->regs->time, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) info->regs->regs_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ret = s5m8767_rtc_set_time_reg(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static int s5m_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct s5m_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u8 data[RTC_MAX_NUM_TIME_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) info->regs->regs_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) switch (info->device_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) case S5M8763X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) s5m8763_data_to_tm(data, &alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = regmap_read(info->regmap, S5M_ALARM0_CONF, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) alrm->enabled = !!val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) case S5M8767X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) case S2MPS15X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) case S2MPS14X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) case S2MPS13X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) s5m8767_data_to_tm(data, &alrm->time, info->rtc_24hr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) alrm->enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) for (i = 0; i < info->regs->regs_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (data[i] & ALARM_ENABLE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) alrm->enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_dbg(dev, "%s: %ptR(%d)\n", __func__, &alrm->time, alrm->time.tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ret = s5m_check_peding_alarm_interrupt(info, alrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static int s5m_rtc_stop_alarm(struct s5m_rtc_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u8 data[RTC_MAX_NUM_TIME_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct rtc_time tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) info->regs->regs_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) s5m8767_data_to_tm(data, &tm, info->rtc_24hr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev_dbg(info->dev, "%s: %ptR(%d)\n", __func__, &tm, tm.tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) switch (info->device_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) case S5M8763X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ret = regmap_write(info->regmap, S5M_ALARM0_CONF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) case S5M8767X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) case S2MPS15X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) case S2MPS14X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) case S2MPS13X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) for (i = 0; i < info->regs->regs_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) data[i] &= ~ALARM_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ret = regmap_raw_write(info->regmap, info->regs->alarm0, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) info->regs->regs_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ret = s5m8767_rtc_set_alarm_reg(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static int s5m_rtc_start_alarm(struct s5m_rtc_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u8 data[RTC_MAX_NUM_TIME_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u8 alarm0_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct rtc_time tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ret = regmap_bulk_read(info->regmap, info->regs->alarm0, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) info->regs->regs_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) s5m8767_data_to_tm(data, &tm, info->rtc_24hr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev_dbg(info->dev, "%s: %ptR(%d)\n", __func__, &tm, tm.tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) switch (info->device_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) case S5M8763X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) alarm0_conf = 0x77;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret = regmap_write(info->regmap, S5M_ALARM0_CONF, alarm0_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) case S5M8767X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) case S2MPS15X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) case S2MPS14X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) case S2MPS13X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) data[RTC_SEC] |= ALARM_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) data[RTC_MIN] |= ALARM_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) data[RTC_HOUR] |= ALARM_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (data[RTC_DATE] & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) data[RTC_DATE] |= ALARM_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (data[RTC_MONTH] & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) data[RTC_MONTH] |= ALARM_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (data[RTC_YEAR1] & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) data[RTC_YEAR1] |= ALARM_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ret = regmap_raw_write(info->regmap, info->regs->alarm0, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) info->regs->regs_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ret = s5m8767_rtc_set_alarm_reg(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static int s5m_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct s5m_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u8 data[RTC_MAX_NUM_TIME_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) switch (info->device_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) case S5M8763X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) s5m8763_tm_to_data(&alrm->time, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) case S5M8767X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) case S2MPS15X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) case S2MPS14X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) case S2MPS13X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) s5m8767_tm_to_data(&alrm->time, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dev_dbg(dev, "%s: %ptR(%d)\n", __func__, &alrm->time, alrm->time.tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ret = s5m_rtc_stop_alarm(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ret = regmap_raw_write(info->regmap, info->regs->alarm0, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) info->regs->regs_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ret = s5m8767_rtc_set_alarm_reg(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (alrm->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ret = s5m_rtc_start_alarm(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static int s5m_rtc_alarm_irq_enable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct s5m_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return s5m_rtc_start_alarm(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return s5m_rtc_stop_alarm(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static irqreturn_t s5m_rtc_alarm_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct s5m_rtc_info *info = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static const struct rtc_class_ops s5m_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .read_time = s5m_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .set_time = s5m_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .read_alarm = s5m_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .set_alarm = s5m_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .alarm_irq_enable = s5m_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int s5m8767_rtc_init_reg(struct s5m_rtc_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u8 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) switch (info->device_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) case S5M8763X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) case S5M8767X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* UDR update time. Default of 7.32 ms is too long. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ret = regmap_update_bits(info->regmap, S5M_RTC_UDR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) S5M_RTC_UDR_T_MASK, S5M_RTC_UDR_T_450_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) dev_err(info->dev, "%s: fail to change UDR time: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* Set RTC control register : Binary mode, 24hour mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ret = regmap_raw_write(info->regmap, S5M_ALARM0_CONF, data, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) case S2MPS15X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case S2MPS14X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) case S2MPS13X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) data[0] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ret = regmap_write(info->regmap, info->regs->ctrl, data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * Should set WUDR & (RUDR or AUDR) bits to high after writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * RTC_CTRL register like writing Alarm registers. We can't find
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * the description from datasheet but vendor code does that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * really.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ret = s5m8767_rtc_set_alarm_reg(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) info->rtc_24hr_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dev_err(info->dev, "%s: fail to write controlm reg(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static int s5m_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct sec_pmic_dev *s5m87xx = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct sec_platform_data *pdata = s5m87xx->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) struct s5m_rtc_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) const struct regmap_config *regmap_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) int ret, alarm_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dev_err(pdev->dev.parent, "Platform data not supplied\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) switch (platform_get_device_id(pdev)->driver_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) case S2MPS15X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) regmap_cfg = &s2mps14_rtc_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) info->regs = &s2mps15_rtc_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) alarm_irq = S2MPS14_IRQ_RTCA0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) case S2MPS14X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) regmap_cfg = &s2mps14_rtc_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) info->regs = &s2mps14_rtc_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) alarm_irq = S2MPS14_IRQ_RTCA0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) case S2MPS13X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) regmap_cfg = &s2mps14_rtc_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) info->regs = &s2mps13_rtc_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) alarm_irq = S2MPS14_IRQ_RTCA0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) case S5M8763X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) regmap_cfg = &s5m_rtc_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) info->regs = &s5m_rtc_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) alarm_irq = S5M8763_IRQ_ALARM0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) case S5M8767X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) regmap_cfg = &s5m_rtc_regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) info->regs = &s5m_rtc_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) alarm_irq = S5M8767_IRQ_RTCA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) "Device type %lu is not supported by RTC driver\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) platform_get_device_id(pdev)->driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) info->i2c = i2c_new_dummy_device(s5m87xx->i2c->adapter, RTC_I2C_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (IS_ERR(info->i2c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) dev_err(&pdev->dev, "Failed to allocate I2C for RTC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return PTR_ERR(info->i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) info->regmap = devm_regmap_init_i2c(info->i2c, regmap_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (IS_ERR(info->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ret = PTR_ERR(info->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev_err(&pdev->dev, "Failed to allocate RTC register map: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) info->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) info->s5m87xx = s5m87xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) info->device_type = platform_get_device_id(pdev)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (s5m87xx->irq_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) info->irq = regmap_irq_get_virq(s5m87xx->irq_data, alarm_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (info->irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) dev_err(&pdev->dev, "Failed to get virtual IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) alarm_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) platform_set_drvdata(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ret = s5m8767_rtc_init_reg(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) info->rtc_dev = devm_rtc_device_register(&pdev->dev, "s5m-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) &s5m_rtc_ops, THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (IS_ERR(info->rtc_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ret = PTR_ERR(info->rtc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (!info->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) dev_info(&pdev->dev, "Alarm IRQ not available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ret = devm_request_threaded_irq(&pdev->dev, info->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) s5m_rtc_alarm_irq, 0, "rtc-alarm0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) info->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) i2c_unregister_device(info->i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static int s5m_rtc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct s5m_rtc_info *info = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) i2c_unregister_device(info->i2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static int s5m_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct s5m_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (info->irq && device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ret = disable_irq_wake(info->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static int s5m_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct s5m_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (info->irq && device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ret = enable_irq_wake(info->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static SIMPLE_DEV_PM_OPS(s5m_rtc_pm_ops, s5m_rtc_suspend, s5m_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static const struct platform_device_id s5m_rtc_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) { "s5m-rtc", S5M8767X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) { "s2mps13-rtc", S2MPS13X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) { "s2mps14-rtc", S2MPS14X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) { "s2mps15-rtc", S2MPS15X },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) MODULE_DEVICE_TABLE(platform, s5m_rtc_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static struct platform_driver s5m_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .name = "s5m-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .pm = &s5m_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .probe = s5m_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .remove = s5m_rtc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .id_table = s5m_rtc_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) module_platform_driver(s5m_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* Module information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) MODULE_DESCRIPTION("Samsung S5M/S2MPS14 RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) MODULE_ALIAS("platform:s5m-rtc");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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