Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *		      http://www.simtec.co.uk/products/SWLINUX/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * S3C2410 Internal RTC register definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef __ASM_ARCH_REGS_RTC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __ASM_ARCH_REGS_RTC_H __FILE__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define S3C2410_RTCREG(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define S3C2410_INTP		S3C2410_RTCREG(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define S3C2410_INTP_ALM	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define S3C2410_INTP_TIC	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define S3C2410_RTCCON		S3C2410_RTCREG(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define S3C2410_RTCCON_RTCEN	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define S3C2410_RTCCON_CNTSEL	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define S3C2410_RTCCON_CLKRST	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define S3C2443_RTCCON_TICSEL	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define S3C64XX_RTCCON_TICEN	(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define S3C2410_TICNT		S3C2410_RTCREG(0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define S3C2410_TICNT_ENABLE	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* S3C2443: tick count is 15 bit wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  * TICNT[6:0] contains upper 7 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  * TICNT1[7:0] contains lower 8 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S3C2443_TICNT_PART(x)	((x & 0x7f00) >> 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define S3C2443_TICNT1		S3C2410_RTCREG(0x4C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define S3C2443_TICNT1_PART(x)	(x & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* S3C2416: tick count is 32 bit wide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  * TICNT[6:0] contains bits [14:8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  * TICNT1[7:0] contains lower 8 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  * TICNT2[16:0] contains upper 17 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define S3C2416_TICNT2		S3C2410_RTCREG(0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define S3C2416_TICNT2_PART(x)	((x & 0xffff8000) >> 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define S3C2410_RTCALM		S3C2410_RTCREG(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define S3C2410_RTCALM_ALMEN	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define S3C2410_RTCALM_YEAREN	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define S3C2410_RTCALM_MONEN	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define S3C2410_RTCALM_DAYEN	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define S3C2410_RTCALM_HOUREN	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define S3C2410_RTCALM_MINEN	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define S3C2410_RTCALM_SECEN	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define S3C2410_ALMSEC		S3C2410_RTCREG(0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define S3C2410_ALMMIN		S3C2410_RTCREG(0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define S3C2410_ALMHOUR		S3C2410_RTCREG(0x5c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define S3C2410_ALMDATE		S3C2410_RTCREG(0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define S3C2410_ALMMON		S3C2410_RTCREG(0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define S3C2410_ALMYEAR		S3C2410_RTCREG(0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define S3C2410_RTCSEC		S3C2410_RTCREG(0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define S3C2410_RTCMIN		S3C2410_RTCREG(0x74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define S3C2410_RTCHOUR		S3C2410_RTCREG(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define S3C2410_RTCDATE		S3C2410_RTCREG(0x7c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define S3C2410_RTCMON		S3C2410_RTCREG(0x84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define S3C2410_RTCYEAR		S3C2410_RTCREG(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif /* __ASM_ARCH_REGS_RTC_H */