^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Seiko Instruments S-35390A RTC Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2007 Byron Bradley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/bitrev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define S35390A_CMD_STATUS1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define S35390A_CMD_STATUS2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define S35390A_CMD_TIME1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define S35390A_CMD_TIME2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define S35390A_CMD_INT2_REG1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define S35390A_BYTE_YEAR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define S35390A_BYTE_MONTH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define S35390A_BYTE_DAY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define S35390A_BYTE_WDAY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define S35390A_BYTE_HOURS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define S35390A_BYTE_MINS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define S35390A_BYTE_SECS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define S35390A_ALRM_BYTE_WDAY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S35390A_ALRM_BYTE_HOURS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define S35390A_ALRM_BYTE_MINS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* flags for STATUS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define S35390A_FLAG_POC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define S35390A_FLAG_BLD BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define S35390A_FLAG_INT2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define S35390A_FLAG_24H BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define S35390A_FLAG_RESET BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* flag for STATUS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define S35390A_FLAG_TEST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* INT2 pin output mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define S35390A_INT2_MODE_MASK 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define S35390A_INT2_MODE_NOINTR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define S35390A_INT2_MODE_ALARM BIT(1) /* INT2AE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define S35390A_INT2_MODE_PMIN_EDG BIT(2) /* INT2ME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define S35390A_INT2_MODE_FREQ BIT(3) /* INT2FE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define S35390A_INT2_MODE_PMIN (BIT(3) | BIT(2)) /* INT2FE | INT2ME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const struct i2c_device_id s35390a_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { "s35390a", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MODULE_DEVICE_TABLE(i2c, s35390a_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const struct of_device_id s35390a_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { .compatible = "s35390a" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { .compatible = "sii,s35390a" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MODULE_DEVICE_TABLE(of, s35390a_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct s35390a {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct i2c_client *client[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int twentyfourhour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int s35390a_set_reg(struct s35390a *s35390a, int reg, char *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct i2c_client *client = s35390a->client[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .len = len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .buf = buf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if ((i2c_transfer(client->adapter, msg, 1)) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int s35390a_get_reg(struct s35390a *s35390a, int reg, char *buf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct i2c_client *client = s35390a->client[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct i2c_msg msg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .len = len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .buf = buf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if ((i2c_transfer(client->adapter, msg, 1)) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int s35390a_init(struct s35390a *s35390a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned initcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * At least one of POC and BLD are set, so reinitialise chip. Keeping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * this information in the hardware to know later that the time isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * valid is unfortunately not possible because POC and BLD are cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * on read. So the reset is best done now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * The 24H bit is kept over reset, so set it already here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) initialize:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) buf = S35390A_FLAG_RESET | S35390A_FLAG_24H;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ret = s35390a_set_reg(s35390a, S35390A_CMD_STATUS1, &buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ret = s35390a_get_reg(s35390a, S35390A_CMD_STATUS1, &buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (buf & (S35390A_FLAG_POC | S35390A_FLAG_BLD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Try up to five times to reset the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (initcount < 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ++initcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) goto initialize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Returns <0 on error, 0 if rtc is setup fine and 1 if the chip was reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * To keep the information if an irq is pending, pass the value read from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * STATUS1 to the caller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int s35390a_read_status(struct s35390a *s35390a, char *status1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ret = s35390a_get_reg(s35390a, S35390A_CMD_STATUS1, status1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (*status1 & S35390A_FLAG_POC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Do not communicate for 0.5 seconds since the power-on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * detection circuit is in operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) msleep(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) } else if (*status1 & S35390A_FLAG_BLD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * If both POC and BLD are unset everything is fine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int s35390a_disable_test_mode(struct s35390a *s35390a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) char buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (s35390a_get_reg(s35390a, S35390A_CMD_STATUS2, buf, sizeof(buf)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (!(buf[0] & S35390A_FLAG_TEST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) buf[0] &= ~S35390A_FLAG_TEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static char s35390a_hr2reg(struct s35390a *s35390a, int hour)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (s35390a->twentyfourhour)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return bin2bcd(hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (hour < 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return bin2bcd(hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return 0x40 | bin2bcd(hour - 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int s35390a_reg2hr(struct s35390a *s35390a, char reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (s35390a->twentyfourhour)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return bcd2bin(reg & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) hour = bcd2bin(reg & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (reg & 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) hour += 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int s35390a_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct s35390a *s35390a = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) char buf[7], status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d mday=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) "mon=%d, year=%d, wday=%d\n", __func__, tm->tm_sec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tm->tm_min, tm->tm_hour, tm->tm_mday, tm->tm_mon, tm->tm_year,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (s35390a_read_status(s35390a, &status) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) s35390a_init(s35390a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) buf[S35390A_BYTE_YEAR] = bin2bcd(tm->tm_year - 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) buf[S35390A_BYTE_MONTH] = bin2bcd(tm->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) buf[S35390A_BYTE_DAY] = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) buf[S35390A_BYTE_WDAY] = bin2bcd(tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) buf[S35390A_BYTE_HOURS] = s35390a_hr2reg(s35390a, tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) buf[S35390A_BYTE_MINS] = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) buf[S35390A_BYTE_SECS] = bin2bcd(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* This chip expects the bits of each byte to be in reverse order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) for (i = 0; i < 7; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) buf[i] = bitrev8(buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) err = s35390a_set_reg(s35390a, S35390A_CMD_TIME1, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int s35390a_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct s35390a *s35390a = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) char buf[7], status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (s35390a_read_status(s35390a, &status) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) err = s35390a_get_reg(s35390a, S35390A_CMD_TIME1, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* This chip returns the bits of each byte in reverse order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) for (i = 0; i < 7; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) buf[i] = bitrev8(buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) tm->tm_sec = bcd2bin(buf[S35390A_BYTE_SECS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) tm->tm_min = bcd2bin(buf[S35390A_BYTE_MINS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) tm->tm_hour = s35390a_reg2hr(s35390a, buf[S35390A_BYTE_HOURS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) tm->tm_wday = bcd2bin(buf[S35390A_BYTE_WDAY]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) tm->tm_mday = bcd2bin(buf[S35390A_BYTE_DAY]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) tm->tm_mon = bcd2bin(buf[S35390A_BYTE_MONTH]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) tm->tm_year = bcd2bin(buf[S35390A_BYTE_YEAR]) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, mday=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "mon=%d, year=%d, wday=%d\n", __func__, tm->tm_sec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) tm->tm_min, tm->tm_hour, tm->tm_mday, tm->tm_mon, tm->tm_year,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int s35390a_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct s35390a *s35390a = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) char buf[3], sts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_dbg(&client->dev, "%s: alm is secs=%d, mins=%d, hours=%d mday=%d, "\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "mon=%d, year=%d, wday=%d\n", __func__, alm->time.tm_sec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) alm->time.tm_min, alm->time.tm_hour, alm->time.tm_mday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) alm->time.tm_mon, alm->time.tm_year, alm->time.tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (alm->time.tm_sec != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev_warn(&client->dev, "Alarms are only supported on a per minute basis!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* disable interrupt (which deasserts the irq line) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) err = s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, &sts, sizeof(sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* clear pending interrupt (in STATUS1 only), if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) err = s35390a_get_reg(s35390a, S35390A_CMD_STATUS1, &sts, sizeof(sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (alm->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) sts = S35390A_INT2_MODE_ALARM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) sts = S35390A_INT2_MODE_NOINTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* set interupt mode*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) err = s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, &sts, sizeof(sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (alm->time.tm_wday != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) buf[S35390A_ALRM_BYTE_WDAY] = bin2bcd(alm->time.tm_wday) | 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) buf[S35390A_ALRM_BYTE_WDAY] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) buf[S35390A_ALRM_BYTE_HOURS] = s35390a_hr2reg(s35390a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) alm->time.tm_hour) | 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) buf[S35390A_ALRM_BYTE_MINS] = bin2bcd(alm->time.tm_min) | 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (alm->time.tm_hour >= 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) buf[S35390A_ALRM_BYTE_HOURS] |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) for (i = 0; i < 3; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) buf[i] = bitrev8(buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) err = s35390a_set_reg(s35390a, S35390A_CMD_INT2_REG1, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int s35390a_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct s35390a *s35390a = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) char buf[3], sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) err = s35390a_get_reg(s35390a, S35390A_CMD_STATUS2, &sts, sizeof(sts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if ((sts & S35390A_INT2_MODE_MASK) != S35390A_INT2_MODE_ALARM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * When the alarm isn't enabled, the register to configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * the alarm time isn't accessible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) alm->enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) alm->enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) err = s35390a_get_reg(s35390a, S35390A_CMD_INT2_REG1, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* This chip returns the bits of each byte in reverse order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) for (i = 0; i < 3; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) buf[i] = bitrev8(buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * B0 of the three matching registers is an enable flag. Iff it is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * the configured value is used for matching.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (buf[S35390A_ALRM_BYTE_WDAY] & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) alm->time.tm_wday =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) bcd2bin(buf[S35390A_ALRM_BYTE_WDAY] & ~0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (buf[S35390A_ALRM_BYTE_HOURS] & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) alm->time.tm_hour =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) s35390a_reg2hr(s35390a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) buf[S35390A_ALRM_BYTE_HOURS] & ~0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (buf[S35390A_ALRM_BYTE_MINS] & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) alm->time.tm_min = bcd2bin(buf[S35390A_ALRM_BYTE_MINS] & ~0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* alarm triggers always at s=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) alm->time.tm_sec = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev_dbg(&client->dev, "%s: alm is mins=%d, hours=%d, wday=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) __func__, alm->time.tm_min, alm->time.tm_hour,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) alm->time.tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int s35390a_rtc_ioctl(struct device *dev, unsigned int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct s35390a *s35390a = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) char sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case RTC_VL_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* s35390a_reset set lowvoltage flag and init RTC if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) err = s35390a_read_status(s35390a, &sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (copy_to_user((void __user *)arg, &err, sizeof(int)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case RTC_VL_CLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* update flag and clear register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) err = s35390a_init(s35390a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static const struct rtc_class_ops s35390a_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .read_time = s35390a_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .set_time = s35390a_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .set_alarm = s35390a_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .read_alarm = s35390a_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .ioctl = s35390a_rtc_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static int s35390a_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int err, err_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct s35390a *s35390a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) char buf, status1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) s35390a = devm_kzalloc(dev, sizeof(struct s35390a), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (!s35390a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) s35390a->client[0] = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) i2c_set_clientdata(client, s35390a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* This chip uses multiple addresses, use dummy devices for them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) for (i = 1; i < 8; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) s35390a->client[i] = devm_i2c_new_dummy_device(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) client->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) client->addr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (IS_ERR(s35390a->client[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dev_err(dev, "Address %02x unavailable\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) client->addr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return PTR_ERR(s35390a->client[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) s35390a->rtc = devm_rtc_allocate_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (IS_ERR(s35390a->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return PTR_ERR(s35390a->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) err_read = s35390a_read_status(s35390a, &status1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (err_read < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev_err(dev, "error resetting chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return err_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (status1 & S35390A_FLAG_24H)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) s35390a->twentyfourhour = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) s35390a->twentyfourhour = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (status1 & S35390A_FLAG_INT2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* disable alarm (and maybe test mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) buf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) err = s35390a_set_reg(s35390a, S35390A_CMD_STATUS2, &buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_err(dev, "error disabling alarm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) err = s35390a_disable_test_mode(s35390a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dev_err(dev, "error disabling test mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) device_set_wakeup_capable(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) s35390a->rtc->ops = &s35390a_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) s35390a->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) s35390a->rtc->range_max = RTC_TIMESTAMP_END_2099;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* supports per-minute alarms only, therefore set uie_unsupported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) s35390a->rtc->uie_unsupported = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (status1 & S35390A_FLAG_INT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) rtc_update_irq(s35390a->rtc, 1, RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return rtc_register_device(s35390a->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static struct i2c_driver s35390a_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .name = "rtc-s35390a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .of_match_table = of_match_ptr(s35390a_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .probe = s35390a_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .id_table = s35390a_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) module_i2c_driver(s35390a_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) MODULE_AUTHOR("Byron Bradley <byron.bbradley@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) MODULE_DESCRIPTION("S35390A RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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