^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* drivers/rtc/rtc-rx4581.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * written by Torben Hohn <torbenh@linutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * drivers/rtc/rtc-max6902.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2006 8D Technologies inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2004 Compulab Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Driver for MAX6902 spi RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * and based on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * drivers/rtc/rtc-rx8581.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * An I2C driver for the Epson RX8581 RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Author: Martyn Welch <martyn.welch@ge.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Based on: rtc-pcf8563.c (An I2C driver for the Philips PCF8563 RTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Copyright 2005-06 Tower Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RX4581_REG_SC 0x00 /* Second in BCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RX4581_REG_MN 0x01 /* Minute in BCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RX4581_REG_HR 0x02 /* Hour in BCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RX4581_REG_DW 0x03 /* Day of Week */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RX4581_REG_DM 0x04 /* Day of Month in BCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RX4581_REG_MO 0x05 /* Month in BCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RX4581_REG_YR 0x06 /* Year in BCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RX4581_REG_RAM 0x07 /* RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RX4581_REG_AMN 0x08 /* Alarm Min in BCD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RX4581_REG_AHR 0x09 /* Alarm Hour in BCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RX4581_REG_ADM 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RX4581_REG_ADW 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RX4581_REG_TMR0 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RX4581_REG_TMR1 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RX4581_REG_EXT 0x0D /* Extension Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RX4581_REG_FLAG 0x0E /* Flag Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RX4581_REG_CTRL 0x0F /* Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Flag Register bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RX4581_FLAG_UF 0x20 /* Update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RX4581_FLAG_TF 0x10 /* Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RX4581_FLAG_AF 0x08 /* Alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RX4581_FLAG_VLF 0x02 /* Voltage Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Control Register bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RX4581_CTRL_UIE 0x20 /* Update Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RX4581_CTRL_TIE 0x10 /* Timer Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RX4581_CTRL_AIE 0x08 /* Alarm Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RX4581_CTRL_STOP 0x02 /* STOP bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RX4581_CTRL_RESET 0x01 /* RESET bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int rx4581_set_reg(struct device *dev, unsigned char address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned char buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* high nibble must be '0' to write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) buf[0] = address & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) buf[1] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return spi_write_then_read(spi, buf, 2, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int rx4581_get_reg(struct device *dev, unsigned char address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned char *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Set MSB to indicate read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *data = address | 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return spi_write_then_read(spi, data, 1, data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * In the routines that deal directly with the rx8581 hardware, we use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int rx4581_get_datetime(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned char date[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned char data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* First we ensure that the "update flag" is not set, we read the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * time and date then re-read the "update flag". If the update flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * has been set, we know that the time has changed during the read so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * we repeat the whole process again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) err = rx4581_get_reg(dev, RX4581_REG_FLAG, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (err != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dev_err(dev, "Unable to read device flags\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* If update flag set, clear it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (data & RX4581_FLAG_UF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) err = rx4581_set_reg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) RX4581_REG_FLAG, (data & ~RX4581_FLAG_UF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (err != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dev_err(dev, "Unable to write device "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "flags\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Now read time and date */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) date[0] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) err = spi_write_then_read(spi, date, 1, date, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) dev_err(dev, "Unable to read date\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Check flag register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) err = rx4581_get_reg(dev, RX4581_REG_FLAG, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (err != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dev_err(dev, "Unable to read device flags\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) } while (data & RX4581_FLAG_UF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (data & RX4581_FLAG_VLF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "low voltage detected, date/time is not reliable.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "%s: raw data is sec=%02x, min=%02x, hr=%02x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "wday=%02x, mday=%02x, mon=%02x, year=%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) date[0], date[1], date[2], date[3], date[4], date[5], date[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) tm->tm_sec = bcd2bin(date[RX4581_REG_SC] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) tm->tm_min = bcd2bin(date[RX4581_REG_MN] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) tm->tm_hour = bcd2bin(date[RX4581_REG_HR] & 0x3F); /* rtc hr 0-23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) tm->tm_wday = ilog2(date[RX4581_REG_DW] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) tm->tm_mday = bcd2bin(date[RX4581_REG_DM] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) tm->tm_mon = bcd2bin(date[RX4581_REG_MO] & 0x1F) - 1; /* rtc mn 1-12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) tm->tm_year = bcd2bin(date[RX4581_REG_YR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (tm->tm_year < 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) tm->tm_year += 100; /* assume we are in 1970...2069 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "mday=%d, mon=%d, year=%d, wday=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) tm->tm_sec, tm->tm_min, tm->tm_hour,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int rx4581_set_datetime(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned char buf[8], data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "mday=%d, mon=%d, year=%d, wday=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) tm->tm_sec, tm->tm_min, tm->tm_hour,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) buf[0] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* hours, minutes and seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) buf[RX4581_REG_SC+1] = bin2bcd(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) buf[RX4581_REG_MN+1] = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) buf[RX4581_REG_HR+1] = bin2bcd(tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) buf[RX4581_REG_DM+1] = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* month, 1 - 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) buf[RX4581_REG_MO+1] = bin2bcd(tm->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* year and century */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) buf[RX4581_REG_YR+1] = bin2bcd(tm->tm_year % 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) buf[RX4581_REG_DW+1] = (0x1 << tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Stop the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) err = rx4581_get_reg(dev, RX4581_REG_CTRL, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (err != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dev_err(dev, "Unable to read control register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) err = rx4581_set_reg(dev, RX4581_REG_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) (data | RX4581_CTRL_STOP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (err != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dev_err(dev, "Unable to write control register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* write register's data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) err = spi_write_then_read(spi, buf, 8, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (err != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dev_err(dev, "Unable to write to date registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* get VLF and clear it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) err = rx4581_get_reg(dev, RX4581_REG_FLAG, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (err != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dev_err(dev, "Unable to read flag register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) err = rx4581_set_reg(dev, RX4581_REG_FLAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) (data & ~(RX4581_FLAG_VLF)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (err != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev_err(dev, "Unable to write flag register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Restart the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) err = rx4581_get_reg(dev, RX4581_REG_CTRL, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (err != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev_err(dev, "Unable to read control register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) err = rx4581_set_reg(dev, RX4581_REG_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) (data & ~(RX4581_CTRL_STOP)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (err != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev_err(dev, "Unable to write control register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const struct rtc_class_ops rx4581_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .read_time = rx4581_get_datetime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .set_time = rx4581_set_datetime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int rx4581_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned char tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) res = rx4581_get_reg(&spi->dev, RX4581_REG_SC, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (res != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) rtc = devm_rtc_device_register(&spi->dev, "rx4581",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) &rx4581_rtc_ops, THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (IS_ERR(rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return PTR_ERR(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) spi_set_drvdata(spi, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const struct spi_device_id rx4581_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { "rx4581", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MODULE_DEVICE_TABLE(spi, rx4581_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static struct spi_driver rx4581_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .name = "rtc-rx4581",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .probe = rx4581_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .id_table = rx4581_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) module_spi_driver(rx4581_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MODULE_DESCRIPTION("rx4581 spi RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MODULE_AUTHOR("Torben Hohn");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MODULE_ALIAS("spi:rtc-rx4581");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags