^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * RTC driver for the Micro Crystal RV3032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Micro Crystal SA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Alexandre Belloni <alexandre.belloni@bootlin.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RV3032_SEC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RV3032_MIN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RV3032_HOUR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RV3032_WDAY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RV3032_DAY 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RV3032_MONTH 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RV3032_YEAR 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RV3032_ALARM_MIN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RV3032_ALARM_HOUR 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RV3032_ALARM_DAY 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RV3032_STATUS 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RV3032_TLSB 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RV3032_TMSB 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RV3032_CTRL1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RV3032_CTRL2 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RV3032_CTRL3 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RV3032_TS_CTRL 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RV3032_CLK_IRQ 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RV3032_EEPROM_ADDR 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RV3032_EEPROM_DATA 0x3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RV3032_EEPROM_CMD 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RV3032_RAM1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RV3032_PMU 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RV3032_OFFSET 0xC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RV3032_CLKOUT1 0xC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RV3032_CLKOUT2 0xC3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RV3032_TREF0 0xC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RV3032_TREF1 0xC5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RV3032_STATUS_VLF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RV3032_STATUS_PORF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RV3032_STATUS_EVF BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RV3032_STATUS_AF BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RV3032_STATUS_TF BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RV3032_STATUS_UF BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RV3032_STATUS_TLF BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RV3032_STATUS_THF BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RV3032_TLSB_CLKF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RV3032_TLSB_EEBUSY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RV3032_TLSB_TEMP GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RV3032_CLKOUT2_HFD_MSK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RV3032_CLKOUT2_FD_MSK GENMASK(6, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RV3032_CLKOUT2_OS BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RV3032_CTRL1_EERD BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RV3032_CTRL1_WADA BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RV3032_CTRL2_STOP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RV3032_CTRL2_EIE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RV3032_CTRL2_AIE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RV3032_CTRL2_TIE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RV3032_CTRL2_UIE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RV3032_CTRL2_CLKIE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RV3032_CTRL2_TSE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RV3032_PMU_TCM GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RV3032_PMU_TCR GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RV3032_PMU_BSM GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RV3032_PMU_NCLKE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RV3032_PMU_BSM_DSM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RV3032_PMU_BSM_LSM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RV3032_OFFSET_MSK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RV3032_EVT_CTRL_TSR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RV3032_EEPROM_CMD_UPDATE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RV3032_EEPROM_CMD_WRITE 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RV3032_EEPROM_CMD_READ 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RV3032_EEPROM_USER 0xCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RV3032_EEBUSY_POLL 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RV3032_EEBUSY_TIMEOUT 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OFFSET_STEP_PPT 238419
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct rv3032_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #ifdef CONFIG_COMMON_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct clk_hw clkout_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static u16 rv3032_trickle_resistors[] = {1000, 2000, 7000, 11000};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static u16 rv3032_trickle_voltages[] = {0, 1750, 3000, 4400};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int rv3032_exit_eerd(struct rv3032_data *rv3032, u32 eerd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (eerd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return regmap_update_bits(rv3032->regmap, RV3032_CTRL1, RV3032_CTRL1_EERD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int rv3032_enter_eerd(struct rv3032_data *rv3032, u32 *eerd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 ctrl1, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ret = regmap_read(rv3032->regmap, RV3032_CTRL1, &ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *eerd = ctrl1 & RV3032_CTRL1_EERD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (*eerd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) RV3032_CTRL1_EERD, RV3032_CTRL1_EERD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) !(status & RV3032_TLSB_EEBUSY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) rv3032_exit_eerd(rv3032, *eerd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int rv3032_update_cfg(struct rv3032_data *rv3032, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int mask, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 status, eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ret = rv3032_enter_eerd(rv3032, &eerd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ret = regmap_update_bits(rv3032->regmap, reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) goto exit_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ret = regmap_write(rv3032->regmap, RV3032_EEPROM_CMD, RV3032_EEPROM_CMD_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) goto exit_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) usleep_range(46000, RV3032_EEBUSY_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) !(status & RV3032_TLSB_EEBUSY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) exit_eerd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) rv3032_exit_eerd(rv3032, eerd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static irqreturn_t rv3032_handle_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct rv3032_data *rv3032 = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned long events = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 status = 0, ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (regmap_read(rv3032->regmap, RV3032_STATUS, &status) < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) status == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (status & RV3032_STATUS_TF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) status |= RV3032_STATUS_TF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ctrl |= RV3032_CTRL2_TIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) events |= RTC_PF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (status & RV3032_STATUS_AF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) status |= RV3032_STATUS_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ctrl |= RV3032_CTRL2_AIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) events |= RTC_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (status & RV3032_STATUS_UF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) status |= RV3032_STATUS_UF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ctrl |= RV3032_CTRL2_UIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) events |= RTC_UF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (events) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) rtc_update_irq(rv3032->rtc, 1, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) regmap_update_bits(rv3032->regmap, RV3032_STATUS, status, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) regmap_update_bits(rv3032->regmap, RV3032_CTRL2, ctrl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int rv3032_get_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct rv3032_data *rv3032 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u8 date[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int ret, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ret = regmap_read(rv3032->regmap, RV3032_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (status & (RV3032_STATUS_PORF | RV3032_STATUS_VLF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = regmap_bulk_read(rv3032->regmap, RV3032_SEC, date, sizeof(date));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) tm->tm_sec = bcd2bin(date[0] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) tm->tm_min = bcd2bin(date[1] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) tm->tm_hour = bcd2bin(date[2] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) tm->tm_wday = date[3] & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) tm->tm_mday = bcd2bin(date[4] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) tm->tm_mon = bcd2bin(date[5] & 0x1f) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) tm->tm_year = bcd2bin(date[6]) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int rv3032_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct rv3032_data *rv3032 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u8 date[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) date[0] = bin2bcd(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) date[1] = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) date[2] = bin2bcd(tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) date[3] = tm->tm_wday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) date[4] = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) date[5] = bin2bcd(tm->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) date[6] = bin2bcd(tm->tm_year - 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret = regmap_bulk_write(rv3032->regmap, RV3032_SEC, date,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) sizeof(date));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ret = regmap_update_bits(rv3032->regmap, RV3032_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) RV3032_STATUS_PORF | RV3032_STATUS_VLF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int rv3032_get_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct rv3032_data *rv3032 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u8 alarmvals[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int status, ctrl, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ret = regmap_bulk_read(rv3032->regmap, RV3032_ALARM_MIN, alarmvals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) sizeof(alarmvals));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ret = regmap_read(rv3032->regmap, RV3032_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ret = regmap_read(rv3032->regmap, RV3032_CTRL2, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) alrm->time.tm_sec = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) alrm->time.tm_min = bcd2bin(alarmvals[0] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) alrm->time.tm_hour = bcd2bin(alarmvals[1] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) alrm->time.tm_mday = bcd2bin(alarmvals[2] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) alrm->enabled = !!(ctrl & RV3032_CTRL2_AIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) alrm->pending = (status & RV3032_STATUS_AF) && alrm->enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int rv3032_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct rv3032_data *rv3032 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u8 alarmvals[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u8 ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* The alarm has no seconds, round up to nearest minute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (alrm->time.tm_sec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) time64_t alarm_time = rtc_tm_to_time64(&alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) alarm_time += 60 - alrm->time.tm_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) rtc_time64_to_tm(alarm_time, &alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) RV3032_CTRL2_AIE | RV3032_CTRL2_UIE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) alarmvals[0] = bin2bcd(alrm->time.tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) alarmvals[1] = bin2bcd(alrm->time.tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) alarmvals[2] = bin2bcd(alrm->time.tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ret = regmap_update_bits(rv3032->regmap, RV3032_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) RV3032_STATUS_AF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ret = regmap_bulk_write(rv3032->regmap, RV3032_ALARM_MIN, alarmvals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) sizeof(alarmvals));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (alrm->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (rv3032->rtc->uie_rtctimer.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ctrl |= RV3032_CTRL2_UIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (rv3032->rtc->aie_timer.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ctrl |= RV3032_CTRL2_AIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) RV3032_CTRL2_UIE | RV3032_CTRL2_AIE, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static int rv3032_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct rv3032_data *rv3032 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int ctrl = 0, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (rv3032->rtc->uie_rtctimer.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ctrl |= RV3032_CTRL2_UIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (rv3032->rtc->aie_timer.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ctrl |= RV3032_CTRL2_AIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ret = regmap_update_bits(rv3032->regmap, RV3032_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) RV3032_STATUS_AF | RV3032_STATUS_UF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) RV3032_CTRL2_UIE | RV3032_CTRL2_AIE, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static int rv3032_read_offset(struct device *dev, long *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct rv3032_data *rv3032 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int ret, value, steps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ret = regmap_read(rv3032->regmap, RV3032_OFFSET, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) steps = sign_extend32(FIELD_GET(RV3032_OFFSET_MSK, value), 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) *offset = DIV_ROUND_CLOSEST(steps * OFFSET_STEP_PPT, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static int rv3032_set_offset(struct device *dev, long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct rv3032_data *rv3032 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) offset = clamp(offset, -7629L, 7391L) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) offset = DIV_ROUND_CLOSEST(offset, OFFSET_STEP_PPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return rv3032_update_cfg(rv3032, RV3032_OFFSET, RV3032_OFFSET_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) FIELD_PREP(RV3032_OFFSET_MSK, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static int rv3032_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct rv3032_data *rv3032 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int status, val = 0, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) case RTC_VL_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ret = regmap_read(rv3032->regmap, RV3032_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (status & (RV3032_STATUS_PORF | RV3032_STATUS_VLF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) val = RTC_VL_DATA_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return put_user(val, (unsigned int __user *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static int rv3032_nvram_write(void *priv, unsigned int offset, void *val, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return regmap_bulk_write(priv, RV3032_RAM1 + offset, val, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static int rv3032_nvram_read(void *priv, unsigned int offset, void *val, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return regmap_bulk_read(priv, RV3032_RAM1 + offset, val, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int rv3032_eeprom_write(void *priv, unsigned int offset, void *val, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct rv3032_data *rv3032 = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u32 status, eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u8 *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ret = rv3032_enter_eerd(rv3032, &eerd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) for (i = 0; i < bytes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ret = regmap_write(rv3032->regmap, RV3032_EEPROM_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) RV3032_EEPROM_USER + offset + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) goto exit_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ret = regmap_write(rv3032->regmap, RV3032_EEPROM_DATA, buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) goto exit_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = regmap_write(rv3032->regmap, RV3032_EEPROM_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) RV3032_EEPROM_CMD_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) goto exit_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) usleep_range(RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) !(status & RV3032_TLSB_EEBUSY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) goto exit_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) exit_eerd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) rv3032_exit_eerd(rv3032, eerd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static int rv3032_eeprom_read(void *priv, unsigned int offset, void *val, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct rv3032_data *rv3032 = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u32 status, eerd, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u8 *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ret = rv3032_enter_eerd(rv3032, &eerd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) for (i = 0; i < bytes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret = regmap_write(rv3032->regmap, RV3032_EEPROM_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) RV3032_EEPROM_USER + offset + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) goto exit_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = regmap_write(rv3032->regmap, RV3032_EEPROM_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) RV3032_EEPROM_CMD_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) goto exit_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) !(status & RV3032_TLSB_EEBUSY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) goto exit_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ret = regmap_read(rv3032->regmap, RV3032_EEPROM_DATA, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) goto exit_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) buf[i] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) exit_eerd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) rv3032_exit_eerd(rv3032, eerd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int rv3032_trickle_charger_setup(struct device *dev, struct rv3032_data *rv3032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u32 val, ohms, voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) val = FIELD_PREP(RV3032_PMU_TCM, 1) | FIELD_PREP(RV3032_PMU_BSM, RV3032_PMU_BSM_DSM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (!device_property_read_u32(dev, "trickle-voltage-millivolt", &voltage)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) for (i = 0; i < ARRAY_SIZE(rv3032_trickle_voltages); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (voltage == rv3032_trickle_voltages[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (i < ARRAY_SIZE(rv3032_trickle_voltages))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) val = FIELD_PREP(RV3032_PMU_TCM, i) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) FIELD_PREP(RV3032_PMU_BSM, RV3032_PMU_BSM_LSM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (device_property_read_u32(dev, "trickle-resistor-ohms", &ohms))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) for (i = 0; i < ARRAY_SIZE(rv3032_trickle_resistors); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (ohms == rv3032_trickle_resistors[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (i >= ARRAY_SIZE(rv3032_trickle_resistors)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) dev_warn(dev, "invalid trickle resistor value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return rv3032_update_cfg(rv3032, RV3032_PMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) RV3032_PMU_TCR | RV3032_PMU_TCM | RV3032_PMU_BSM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) val | FIELD_PREP(RV3032_PMU_TCR, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #ifdef CONFIG_COMMON_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define clkout_hw_to_rv3032(hw) container_of(hw, struct rv3032_data, clkout_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static int clkout_xtal_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 32768,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define RV3032_HFD_STEP 8192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static unsigned long rv3032_clkout_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) int clkout, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ret = regmap_read(rv3032->regmap, RV3032_CLKOUT2, &clkout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (clkout & RV3032_CLKOUT2_OS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) unsigned long rate = FIELD_GET(RV3032_CLKOUT2_HFD_MSK, clkout) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ret = regmap_read(rv3032->regmap, RV3032_CLKOUT1, &clkout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) rate += clkout + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return rate * RV3032_HFD_STEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return clkout_xtal_rates[FIELD_GET(RV3032_CLKOUT2_FD_MSK, clkout)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static long rv3032_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) int i, hfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (rate < RV3032_HFD_STEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) for (i = 0; i < ARRAY_SIZE(clkout_xtal_rates); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (clkout_xtal_rates[i] <= rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return clkout_xtal_rates[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) hfd = DIV_ROUND_CLOSEST(rate, RV3032_HFD_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return RV3032_HFD_STEP * clamp(hfd, 0, 8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static int rv3032_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) u32 status, eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) int i, hfd, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) for (i = 0; i < ARRAY_SIZE(clkout_xtal_rates); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (clkout_xtal_rates[i] == rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return rv3032_update_cfg(rv3032, RV3032_CLKOUT2, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) FIELD_PREP(RV3032_CLKOUT2_FD_MSK, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) hfd = DIV_ROUND_CLOSEST(rate, RV3032_HFD_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) hfd = clamp(hfd, 1, 8192) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ret = rv3032_enter_eerd(rv3032, &eerd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ret = regmap_write(rv3032->regmap, RV3032_CLKOUT1, hfd & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) goto exit_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ret = regmap_write(rv3032->regmap, RV3032_CLKOUT2, RV3032_CLKOUT2_OS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) FIELD_PREP(RV3032_CLKOUT2_HFD_MSK, hfd >> 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) goto exit_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ret = regmap_write(rv3032->regmap, RV3032_EEPROM_CMD, RV3032_EEPROM_CMD_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) goto exit_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) usleep_range(46000, RV3032_EEBUSY_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ret = regmap_read_poll_timeout(rv3032->regmap, RV3032_TLSB, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) !(status & RV3032_TLSB_EEBUSY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) RV3032_EEBUSY_POLL, RV3032_EEBUSY_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) exit_eerd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) rv3032_exit_eerd(rv3032, eerd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static int rv3032_clkout_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return rv3032_update_cfg(rv3032, RV3032_PMU, RV3032_PMU_NCLKE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static void rv3032_clkout_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) rv3032_update_cfg(rv3032, RV3032_PMU, RV3032_PMU_NCLKE, RV3032_PMU_NCLKE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static int rv3032_clkout_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) int val, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct rv3032_data *rv3032 = clkout_hw_to_rv3032(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ret = regmap_read(rv3032->regmap, RV3032_PMU, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return !(val & RV3032_PMU_NCLKE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static const struct clk_ops rv3032_clkout_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .prepare = rv3032_clkout_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .unprepare = rv3032_clkout_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .is_prepared = rv3032_clkout_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .recalc_rate = rv3032_clkout_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .round_rate = rv3032_clkout_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .set_rate = rv3032_clkout_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static int rv3032_clkout_register_clk(struct rv3032_data *rv3032,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct device_node *node = client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ret = regmap_update_bits(rv3032->regmap, RV3032_TLSB, RV3032_TLSB_CLKF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL2, RV3032_CTRL2_CLKIE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ret = regmap_write(rv3032->regmap, RV3032_CLK_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) init.name = "rv3032-clkout";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) init.ops = &rv3032_clkout_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) init.parent_names = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) init.num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) rv3032->clkout_hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) of_property_read_string(node, "clock-output-names", &init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) clk = devm_clk_register(&client->dev, &rv3032->clkout_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (!IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) of_clk_add_provider(node, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static int rv3032_hwmon_read_temp(struct device *dev, long *mC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct rv3032_data *rv3032 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) int temp, prev = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ret = regmap_bulk_read(rv3032->regmap, RV3032_TLSB, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) temp = sign_extend32(buf[1], 7) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) temp |= FIELD_GET(RV3032_TLSB_TEMP, buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* No blocking or shadowing on RV3032_TLSB and RV3032_TMSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) prev = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ret = regmap_bulk_read(rv3032->regmap, RV3032_TLSB, buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) temp = sign_extend32(buf[1], 7) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) temp |= FIELD_GET(RV3032_TLSB_TEMP, buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) } while (temp != prev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) *mC = (temp * 1000) / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static umode_t rv3032_hwmon_is_visible(const void *data, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (type != hwmon_temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static int rv3032_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) u32 attr, int channel, long *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) err = rv3032_hwmon_read_temp(dev, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) err = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static const struct hwmon_channel_info *rv3032_hwmon_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static const struct hwmon_ops rv3032_hwmon_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .is_visible = rv3032_hwmon_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .read = rv3032_hwmon_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static const struct hwmon_chip_info rv3032_hwmon_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .ops = &rv3032_hwmon_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .info = rv3032_hwmon_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static void rv3032_hwmon_register(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct rv3032_data *rv3032 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (!IS_REACHABLE(CONFIG_HWMON))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) devm_hwmon_device_register_with_info(dev, "rv3032", rv3032, &rv3032_hwmon_chip_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static struct rtc_class_ops rv3032_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .read_time = rv3032_get_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .set_time = rv3032_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .read_offset = rv3032_read_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .set_offset = rv3032_set_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .ioctl = rv3032_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static const struct regmap_config regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .max_register = 0xCA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static int rv3032_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct rv3032_data *rv3032;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) int ret, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct nvmem_config nvmem_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .name = "rv3032_nvram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .word_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .size = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .type = NVMEM_TYPE_BATTERY_BACKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .reg_read = rv3032_nvram_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .reg_write = rv3032_nvram_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct nvmem_config eeprom_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .name = "rv3032_eeprom",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .word_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .size = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .type = NVMEM_TYPE_EEPROM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .reg_read = rv3032_eeprom_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .reg_write = rv3032_eeprom_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) rv3032 = devm_kzalloc(&client->dev, sizeof(struct rv3032_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (!rv3032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) rv3032->regmap = devm_regmap_init_i2c(client, ®map_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (IS_ERR(rv3032->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return PTR_ERR(rv3032->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) i2c_set_clientdata(client, rv3032);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ret = regmap_read(rv3032->regmap, RV3032_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) rv3032->rtc = devm_rtc_allocate_device(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (IS_ERR(rv3032->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return PTR_ERR(rv3032->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (client->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ret = devm_request_threaded_irq(&client->dev, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) NULL, rv3032_handle_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) IRQF_TRIGGER_LOW | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) "rv3032", rv3032);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) client->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) rv3032_rtc_ops.read_alarm = rv3032_get_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) rv3032_rtc_ops.set_alarm = rv3032_set_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) rv3032_rtc_ops.alarm_irq_enable = rv3032_alarm_irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ret = regmap_update_bits(rv3032->regmap, RV3032_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) RV3032_CTRL1_WADA, RV3032_CTRL1_WADA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) rv3032_trickle_charger_setup(&client->dev, rv3032);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) rv3032->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) rv3032->rtc->range_max = RTC_TIMESTAMP_END_2099;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) rv3032->rtc->ops = &rv3032_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ret = rtc_register_device(rv3032->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) nvmem_cfg.priv = rv3032;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) rtc_nvmem_register(rv3032->rtc, &nvmem_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) eeprom_cfg.priv = rv3032;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) rtc_nvmem_register(rv3032->rtc, &eeprom_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) rv3032->rtc->max_user_freq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #ifdef CONFIG_COMMON_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) rv3032_clkout_register_clk(rv3032, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) rv3032_hwmon_register(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static const struct of_device_id rv3032_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) { .compatible = "microcrystal,rv3032", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) MODULE_DEVICE_TABLE(of, rv3032_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static struct i2c_driver rv3032_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .name = "rtc-rv3032",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .of_match_table = of_match_ptr(rv3032_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .probe_new = rv3032_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) module_i2c_driver(rv3032_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) MODULE_DESCRIPTION("Micro Crystal RV3032 RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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