^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Micro Crystal RV-3029 / RV-3049 rtc class driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Gregory Hermant <gregory.hermant@calao-systems.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Michael Buesch <m@bues.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * based on previously existing rtc class drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Register map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* control section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RV3029_ONOFF_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RV3029_ONOFF_CTRL_WE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RV3029_ONOFF_CTRL_TE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RV3029_ONOFF_CTRL_TAR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RV3029_ONOFF_CTRL_EERE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RV3029_ONOFF_CTRL_SRON BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RV3029_ONOFF_CTRL_TD0 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RV3029_ONOFF_CTRL_TD1 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RV3029_ONOFF_CTRL_CLKINT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RV3029_IRQ_CTRL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RV3029_IRQ_CTRL_AIE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RV3029_IRQ_CTRL_TIE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RV3029_IRQ_CTRL_V1IE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RV3029_IRQ_CTRL_V2IE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RV3029_IRQ_CTRL_SRIE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RV3029_IRQ_FLAGS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RV3029_IRQ_FLAGS_AF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RV3029_IRQ_FLAGS_TF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RV3029_IRQ_FLAGS_V1IF BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RV3029_IRQ_FLAGS_V2IF BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RV3029_IRQ_FLAGS_SRF BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RV3029_STATUS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RV3029_STATUS_VLOW1 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RV3029_STATUS_VLOW2 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RV3029_STATUS_SR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RV3029_STATUS_PON BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RV3029_STATUS_EEBUSY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RV3029_RST_CTRL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RV3029_RST_CTRL_SYSR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RV3029_CONTROL_SECTION_LEN 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* watch section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RV3029_W_SEC 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RV3029_W_MINUTES 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RV3029_W_HOURS 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RV3029_REG_HR_12_24 BIT(6) /* 24h/12h mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RV3029_REG_HR_PM BIT(5) /* PM/AM bit in 12h mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RV3029_W_DATE 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RV3029_W_DAYS 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RV3029_W_MONTHS 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RV3029_W_YEARS 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RV3029_WATCH_SECTION_LEN 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* alarm section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RV3029_A_SC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RV3029_A_MN 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RV3029_A_HR 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RV3029_A_DT 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RV3029_A_DW 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RV3029_A_MO 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RV3029_A_YR 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RV3029_A_AE_X BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RV3029_ALARM_SECTION_LEN 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* timer section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RV3029_TIMER_LOW 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RV3029_TIMER_HIGH 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* temperature section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RV3029_TEMP_PAGE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* eeprom data section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RV3029_E2P_EEDATA1 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RV3029_E2P_EEDATA2 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RV3029_E2PDATA_SECTION_LEN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* eeprom control section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RV3029_CONTROL_E2P_EECTRL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RV3029_EECTRL_THP BIT(0) /* temp scan interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RV3029_EECTRL_THE BIT(1) /* thermometer enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RV3029_EECTRL_FD0 BIT(2) /* CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RV3029_EECTRL_FD1 BIT(3) /* CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RV3029_TRICKLE_1K BIT(4) /* 1.5K resistance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RV3029_TRICKLE_5K BIT(5) /* 5K resistance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RV3029_TRICKLE_20K BIT(6) /* 20K resistance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RV3029_TRICKLE_80K BIT(7) /* 80K resistance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RV3029_TRICKLE_MASK (RV3029_TRICKLE_1K |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) RV3029_TRICKLE_5K |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) RV3029_TRICKLE_20K |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) RV3029_TRICKLE_80K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RV3029_TRICKLE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RV3029_CONTROL_E2P_XOFFS 0x31 /* XTAL offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RV3029_CONTROL_E2P_XOFFS_SIGN BIT(7) /* Sign: 1->pos, 0->neg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RV3029_CONTROL_E2P_QCOEF 0x32 /* XTAL temp drift coef */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RV3029_CONTROL_E2P_TURNOVER 0x33 /* XTAL turnover temp (in *C) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RV3029_CONTROL_E2P_TOV_MASK 0x3F /* XTAL turnover temp mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* user ram section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RV3029_RAM_PAGE 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RV3029_RAM_SECTION_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct rv3029_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int rv3029_eeprom_busywait(struct rv3029_data *rv3029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) for (i = 100; i > 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ret = regmap_read(rv3029->regmap, RV3029_STATUS, &sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (!(sr & RV3029_STATUS_EEBUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) usleep_range(1000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (i <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) dev_err(rv3029->dev, "EEPROM busy wait timeout.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int rv3029_eeprom_exit(struct rv3029_data *rv3029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Re-enable eeprom refresh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return regmap_update_bits(rv3029->regmap, RV3029_ONOFF_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) RV3029_ONOFF_CTRL_EERE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) RV3029_ONOFF_CTRL_EERE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int rv3029_eeprom_enter(struct rv3029_data *rv3029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned int sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Check whether we are in the allowed voltage range. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = regmap_read(rv3029->regmap, RV3029_STATUS, &sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (sr & RV3029_STATUS_VLOW2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (sr & RV3029_STATUS_VLOW1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* We clear the bits and retry once just in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * we had a brown out in early startup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ret = regmap_update_bits(rv3029->regmap, RV3029_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) RV3029_STATUS_VLOW1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) usleep_range(1000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ret = regmap_read(rv3029->regmap, RV3029_STATUS, &sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (sr & RV3029_STATUS_VLOW1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dev_err(rv3029->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "Supply voltage is too low to safely access the EEPROM.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Disable eeprom refresh. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ret = regmap_update_bits(rv3029->regmap, RV3029_ONOFF_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) RV3029_ONOFF_CTRL_EERE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Wait for any previous eeprom accesses to finish. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ret = rv3029_eeprom_busywait(rv3029);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) rv3029_eeprom_exit(rv3029);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int rv3029_eeprom_read(struct rv3029_data *rv3029, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u8 buf[], size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int ret, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) err = rv3029_eeprom_enter(rv3029);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ret = regmap_bulk_read(rv3029->regmap, reg, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) err = rv3029_eeprom_exit(rv3029);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int rv3029_eeprom_write(struct rv3029_data *rv3029, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u8 const buf[], size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int ret, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) err = rv3029_eeprom_enter(rv3029);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) for (i = 0; i < len; i++, reg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret = regmap_read(rv3029->regmap, reg, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (tmp != buf[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) tmp = buf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = regmap_write(rv3029->regmap, reg, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ret = rv3029_eeprom_busywait(rv3029);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) err = rv3029_eeprom_exit(rv3029);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int rv3029_eeprom_update_bits(struct rv3029_data *rv3029,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u8 reg, u8 mask, u8 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u8 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = rv3029_eeprom_read(rv3029, reg, &buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) buf &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) buf |= set & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ret = rv3029_eeprom_write(rv3029, reg, &buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static irqreturn_t rv3029_handle_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct device *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct rv3029_data *rv3029 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct mutex *lock = &rv3029->rtc->ops_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned int flags, controls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned long events = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) mutex_lock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ret = regmap_read(rv3029->regmap, RV3029_IRQ_CTRL, &controls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dev_warn(dev, "Read IRQ Control Register error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mutex_unlock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ret = regmap_read(rv3029->regmap, RV3029_IRQ_FLAGS, &flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dev_warn(dev, "Read IRQ Flags Register error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) mutex_unlock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (flags & RV3029_IRQ_FLAGS_AF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) flags &= ~RV3029_IRQ_FLAGS_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) controls &= ~RV3029_IRQ_CTRL_AIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) events |= RTC_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (events) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) rtc_update_irq(rv3029->rtc, 1, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) regmap_write(rv3029->regmap, RV3029_IRQ_FLAGS, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) regmap_write(rv3029->regmap, RV3029_IRQ_CTRL, controls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) mutex_unlock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int rv3029_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct rv3029_data *rv3029 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned int sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u8 regs[RV3029_WATCH_SECTION_LEN] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ret = regmap_read(rv3029->regmap, RV3029_STATUS, &sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (sr & (RV3029_STATUS_VLOW2 | RV3029_STATUS_PON))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ret = regmap_bulk_read(rv3029->regmap, RV3029_W_SEC, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) RV3029_WATCH_SECTION_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) tm->tm_sec = bcd2bin(regs[RV3029_W_SEC - RV3029_W_SEC]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) tm->tm_min = bcd2bin(regs[RV3029_W_MINUTES - RV3029_W_SEC]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* HR field has a more complex interpretation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) const u8 _hr = regs[RV3029_W_HOURS - RV3029_W_SEC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (_hr & RV3029_REG_HR_12_24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* 12h format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) tm->tm_hour = bcd2bin(_hr & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (_hr & RV3029_REG_HR_PM) /* PM flag set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) tm->tm_hour += 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) } else /* 24h format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) tm->tm_hour = bcd2bin(_hr & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) tm->tm_mday = bcd2bin(regs[RV3029_W_DATE - RV3029_W_SEC]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) tm->tm_mon = bcd2bin(regs[RV3029_W_MONTHS - RV3029_W_SEC]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) tm->tm_year = bcd2bin(regs[RV3029_W_YEARS - RV3029_W_SEC]) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) tm->tm_wday = bcd2bin(regs[RV3029_W_DAYS - RV3029_W_SEC]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static int rv3029_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct rv3029_data *rv3029 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct rtc_time *const tm = &alarm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) unsigned int controls, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u8 regs[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ret = regmap_bulk_read(rv3029->regmap, RV3029_A_SC, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) RV3029_ALARM_SECTION_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ret = regmap_read(rv3029->regmap, RV3029_IRQ_CTRL, &controls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ret = regmap_read(rv3029->regmap, RV3029_IRQ_FLAGS, &flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) tm->tm_sec = bcd2bin(regs[RV3029_A_SC - RV3029_A_SC] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) tm->tm_min = bcd2bin(regs[RV3029_A_MN - RV3029_A_SC] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) tm->tm_hour = bcd2bin(regs[RV3029_A_HR - RV3029_A_SC] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) tm->tm_mday = bcd2bin(regs[RV3029_A_DT - RV3029_A_SC] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) tm->tm_mon = bcd2bin(regs[RV3029_A_MO - RV3029_A_SC] & 0x1f) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) tm->tm_year = bcd2bin(regs[RV3029_A_YR - RV3029_A_SC] & 0x7f) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) tm->tm_wday = bcd2bin(regs[RV3029_A_DW - RV3029_A_SC] & 0x07) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) alarm->enabled = !!(controls & RV3029_IRQ_CTRL_AIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) alarm->pending = (flags & RV3029_IRQ_FLAGS_AF) && alarm->enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int rv3029_alarm_irq_enable(struct device *dev, unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct rv3029_data *rv3029 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return regmap_update_bits(rv3029->regmap, RV3029_IRQ_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) RV3029_IRQ_CTRL_AIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) enable ? RV3029_IRQ_CTRL_AIE : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int rv3029_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct rv3029_data *rv3029 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct rtc_time *const tm = &alarm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u8 regs[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Activate all the alarms with AE_x bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) regs[RV3029_A_SC - RV3029_A_SC] = bin2bcd(tm->tm_sec) | RV3029_A_AE_X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) regs[RV3029_A_MN - RV3029_A_SC] = bin2bcd(tm->tm_min) | RV3029_A_AE_X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) regs[RV3029_A_HR - RV3029_A_SC] = (bin2bcd(tm->tm_hour) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) | RV3029_A_AE_X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) regs[RV3029_A_DT - RV3029_A_SC] = (bin2bcd(tm->tm_mday) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) | RV3029_A_AE_X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) regs[RV3029_A_MO - RV3029_A_SC] = (bin2bcd(tm->tm_mon + 1) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) | RV3029_A_AE_X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) regs[RV3029_A_DW - RV3029_A_SC] = (bin2bcd(tm->tm_wday + 1) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) | RV3029_A_AE_X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) regs[RV3029_A_YR - RV3029_A_SC] = (bin2bcd(tm->tm_year - 100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) | RV3029_A_AE_X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Write the alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ret = regmap_bulk_write(rv3029->regmap, RV3029_A_SC, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) RV3029_ALARM_SECTION_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return rv3029_alarm_irq_enable(dev, alarm->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int rv3029_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct rv3029_data *rv3029 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u8 regs[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) regs[RV3029_W_SEC - RV3029_W_SEC] = bin2bcd(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) regs[RV3029_W_MINUTES - RV3029_W_SEC] = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) regs[RV3029_W_HOURS - RV3029_W_SEC] = bin2bcd(tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) regs[RV3029_W_DATE - RV3029_W_SEC] = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) regs[RV3029_W_MONTHS - RV3029_W_SEC] = bin2bcd(tm->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) regs[RV3029_W_DAYS - RV3029_W_SEC] = bin2bcd(tm->tm_wday + 1) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) regs[RV3029_W_YEARS - RV3029_W_SEC] = bin2bcd(tm->tm_year - 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = regmap_bulk_write(rv3029->regmap, RV3029_W_SEC, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) RV3029_WATCH_SECTION_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* clear PON and VLOW2 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return regmap_update_bits(rv3029->regmap, RV3029_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) RV3029_STATUS_PON | RV3029_STATUS_VLOW2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int rv3029_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct rv3029_data *rv3029 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unsigned long vl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int sr, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) case RTC_VL_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ret = regmap_read(rv3029->regmap, RV3029_STATUS, &sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (sr & RV3029_STATUS_VLOW1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) vl = RTC_VL_ACCURACY_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (sr & (RV3029_STATUS_VLOW2 | RV3029_STATUS_PON))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) vl |= RTC_VL_DATA_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return put_user(vl, (unsigned int __user *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) case RTC_VL_CLR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return regmap_update_bits(rv3029->regmap, RV3029_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) RV3029_STATUS_VLOW1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int rv3029_nvram_write(void *priv, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return regmap_bulk_write(priv, RV3029_RAM_PAGE + offset, val, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int rv3029_nvram_read(void *priv, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return regmap_bulk_read(priv, RV3029_RAM_PAGE + offset, val, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static const struct rv3029_trickle_tab_elem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u32 r; /* resistance in ohms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u8 conf; /* trickle config bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) } rv3029_trickle_tab[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .r = 1076,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .conf = RV3029_TRICKLE_1K | RV3029_TRICKLE_5K |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) RV3029_TRICKLE_20K | RV3029_TRICKLE_80K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .r = 1091,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .conf = RV3029_TRICKLE_1K | RV3029_TRICKLE_5K |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) RV3029_TRICKLE_20K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .r = 1137,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .conf = RV3029_TRICKLE_1K | RV3029_TRICKLE_5K |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) RV3029_TRICKLE_80K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .r = 1154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .conf = RV3029_TRICKLE_1K | RV3029_TRICKLE_5K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .r = 1371,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .conf = RV3029_TRICKLE_1K | RV3029_TRICKLE_20K |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) RV3029_TRICKLE_80K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .r = 1395,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .conf = RV3029_TRICKLE_1K | RV3029_TRICKLE_20K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .r = 1472,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .conf = RV3029_TRICKLE_1K | RV3029_TRICKLE_80K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .r = 1500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .conf = RV3029_TRICKLE_1K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .r = 3810,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .conf = RV3029_TRICKLE_5K | RV3029_TRICKLE_20K |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) RV3029_TRICKLE_80K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .r = 4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .conf = RV3029_TRICKLE_5K | RV3029_TRICKLE_20K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .r = 4706,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .conf = RV3029_TRICKLE_5K | RV3029_TRICKLE_80K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .r = 5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .conf = RV3029_TRICKLE_5K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .r = 16000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .conf = RV3029_TRICKLE_20K | RV3029_TRICKLE_80K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .r = 20000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .conf = RV3029_TRICKLE_20K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .r = 80000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .conf = RV3029_TRICKLE_80K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static void rv3029_trickle_config(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct rv3029_data *rv3029 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct device_node *of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) const struct rv3029_trickle_tab_elem *elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 ohms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u8 trickle_set_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (!of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* Configure the trickle charger. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) err = of_property_read_u32(of_node, "trickle-resistor-ohms", &ohms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Disable trickle charger. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) trickle_set_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Enable trickle charger. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) for (i = 0; i < ARRAY_SIZE(rv3029_trickle_tab); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) elem = &rv3029_trickle_tab[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (elem->r >= ohms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) trickle_set_bits = elem->conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) "Trickle charger enabled at %d ohms resistance.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) elem->r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) err = rv3029_eeprom_update_bits(rv3029, RV3029_CONTROL_E2P_EECTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) RV3029_TRICKLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) trickle_set_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dev_err(dev, "Failed to update trickle charger config\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #ifdef CONFIG_RTC_DRV_RV3029_HWMON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static int rv3029_read_temp(struct rv3029_data *rv3029, int *temp_mC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) unsigned int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ret = regmap_read(rv3029->regmap, RV3029_TEMP_PAGE, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) *temp_mC = ((int)temp - 60) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static ssize_t rv3029_hwmon_show_temp(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct rv3029_data *rv3029 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int ret, temp_mC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ret = rv3029_read_temp(rv3029, &temp_mC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return sprintf(buf, "%d\n", temp_mC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static ssize_t rv3029_hwmon_set_update_interval(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct rv3029_data *rv3029 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) unsigned int th_set_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) unsigned long interval_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ret = kstrtoul(buf, 10, &interval_ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (interval_ms != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) th_set_bits |= RV3029_EECTRL_THE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (interval_ms >= 16000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) th_set_bits |= RV3029_EECTRL_THP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ret = rv3029_eeprom_update_bits(rv3029, RV3029_CONTROL_E2P_EECTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) RV3029_EECTRL_THE | RV3029_EECTRL_THP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) th_set_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static ssize_t rv3029_hwmon_show_update_interval(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct rv3029_data *rv3029 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int ret, interval_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u8 eectrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ret = rv3029_eeprom_read(rv3029, RV3029_CONTROL_E2P_EECTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) &eectrl, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (eectrl & RV3029_EECTRL_THE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (eectrl & RV3029_EECTRL_THP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) interval_ms = 16000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) interval_ms = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) interval_ms = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return sprintf(buf, "%d\n", interval_ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, rv3029_hwmon_show_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static SENSOR_DEVICE_ATTR(update_interval, S_IWUSR | S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) rv3029_hwmon_show_update_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) rv3029_hwmon_set_update_interval, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static struct attribute *rv3029_hwmon_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) &sensor_dev_attr_temp1_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) &sensor_dev_attr_update_interval.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ATTRIBUTE_GROUPS(rv3029_hwmon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static void rv3029_hwmon_register(struct device *dev, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct rv3029_data *rv3029 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) hwmon_dev = devm_hwmon_device_register_with_groups(dev, name, rv3029,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) rv3029_hwmon_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (IS_ERR(hwmon_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) dev_warn(dev, "unable to register hwmon device %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) PTR_ERR(hwmon_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #else /* CONFIG_RTC_DRV_RV3029_HWMON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static void rv3029_hwmon_register(struct device *dev, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #endif /* CONFIG_RTC_DRV_RV3029_HWMON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static struct rtc_class_ops rv3029_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .read_time = rv3029_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .set_time = rv3029_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .ioctl = rv3029_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static int rv3029_probe(struct device *dev, struct regmap *regmap, int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct rv3029_data *rv3029;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct nvmem_config nvmem_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .name = "rv3029_nvram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .word_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .size = RV3029_RAM_SECTION_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .type = NVMEM_TYPE_BATTERY_BACKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .reg_read = rv3029_nvram_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .reg_write = rv3029_nvram_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) rv3029 = devm_kzalloc(dev, sizeof(*rv3029), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (!rv3029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) rv3029->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) rv3029->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) rv3029->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) dev_set_drvdata(dev, rv3029);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) rv3029_trickle_config(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) rv3029_hwmon_register(dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) rv3029->rtc = devm_rtc_allocate_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (IS_ERR(rv3029->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return PTR_ERR(rv3029->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (rv3029->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) rc = devm_request_threaded_irq(dev, rv3029->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) NULL, rv3029_handle_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) IRQF_TRIGGER_LOW | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) "rv3029", dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) dev_warn(dev, "unable to request IRQ, alarms disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) rv3029->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) rv3029_rtc_ops.read_alarm = rv3029_read_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) rv3029_rtc_ops.set_alarm = rv3029_set_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) rv3029_rtc_ops.alarm_irq_enable = rv3029_alarm_irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) rv3029->rtc->ops = &rv3029_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) rv3029->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) rv3029->rtc->range_max = RTC_TIMESTAMP_END_2079;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) rc = rtc_register_device(rv3029->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) nvmem_cfg.priv = rv3029->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) rtc_nvmem_register(rv3029->rtc, &nvmem_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static const struct regmap_range rv3029_holes_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) regmap_reg_range(0x05, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) regmap_reg_range(0x0f, 0x0f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) regmap_reg_range(0x17, 0x17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) regmap_reg_range(0x1a, 0x1f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) regmap_reg_range(0x21, 0x27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) regmap_reg_range(0x34, 0x37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static const struct regmap_access_table rv3029_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .no_ranges = rv3029_holes_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .n_no_ranges = ARRAY_SIZE(rv3029_holes_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static const struct regmap_config config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .rd_table = &rv3029_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .wr_table = &rv3029_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .max_register = 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #if IS_ENABLED(CONFIG_I2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static int rv3029_i2c_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_I2C_BLOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) I2C_FUNC_SMBUS_BYTE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) dev_err(&client->dev, "Adapter does not support SMBUS_I2C_BLOCK or SMBUS_I2C_BYTE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) regmap = devm_regmap_init_i2c(client, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return rv3029_probe(&client->dev, regmap, client->irq, client->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static const struct i2c_device_id rv3029_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) { "rv3029", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) { "rv3029c2", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) MODULE_DEVICE_TABLE(i2c, rv3029_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static const struct of_device_id rv3029_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) { .compatible = "microcrystal,rv3029" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) MODULE_DEVICE_TABLE(of, rv3029_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static struct i2c_driver rv3029_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .name = "rv3029",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .of_match_table = of_match_ptr(rv3029_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .probe = rv3029_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .id_table = rv3029_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static int __init rv3029_register_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return i2c_add_driver(&rv3029_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static void rv3029_unregister_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) i2c_del_driver(&rv3029_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static int __init rv3029_register_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static void rv3029_unregister_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #if IS_ENABLED(CONFIG_SPI_MASTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static int rv3049_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) regmap = devm_regmap_init_spi(spi, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return rv3029_probe(&spi->dev, regmap, spi->irq, "rv3049");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static struct spi_driver rv3049_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .name = "rv3049",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .probe = rv3049_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static int __init rv3049_register_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return spi_register_driver(&rv3049_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static void __exit rv3049_unregister_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) spi_unregister_driver(&rv3049_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static int __init rv3049_register_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static void __exit rv3049_unregister_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static int __init rv30x9_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ret = rv3029_register_driver();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) ret = rv3049_register_driver();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) rv3029_unregister_driver();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) module_init(rv30x9_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static void __exit rv30x9_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) rv3049_unregister_driver();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) rv3029_unregister_driver();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) module_exit(rv30x9_exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) MODULE_AUTHOR("Gregory Hermant <gregory.hermant@calao-systems.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) MODULE_AUTHOR("Michael Buesch <m@bues.ch>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) MODULE_DESCRIPTION("Micro Crystal RV3029/RV3049 RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) MODULE_ALIAS("spi:rv3049");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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