^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * RTC driver for the Micro Crystal RV3028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2019 Micro Crystal SA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Alexandre Belloni <alexandre.belloni@bootlin.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RV3028_SEC 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RV3028_MIN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RV3028_HOUR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RV3028_WDAY 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RV3028_DAY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RV3028_MONTH 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RV3028_YEAR 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RV3028_ALARM_MIN 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RV3028_ALARM_HOUR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RV3028_ALARM_DAY 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RV3028_STATUS 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RV3028_CTRL1 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RV3028_CTRL2 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RV3028_EVT_CTRL 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RV3028_TS_COUNT 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RV3028_TS_SEC 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RV3028_RAM1 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RV3028_EEPROM_ADDR 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RV3028_EEPROM_DATA 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RV3028_EEPROM_CMD 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RV3028_CLKOUT 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RV3028_OFFSET 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RV3028_BACKUP 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RV3028_STATUS_PORF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RV3028_STATUS_EVF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RV3028_STATUS_AF BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RV3028_STATUS_TF BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RV3028_STATUS_UF BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RV3028_STATUS_BSF BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RV3028_STATUS_CLKF BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RV3028_STATUS_EEBUSY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RV3028_CLKOUT_FD_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RV3028_CLKOUT_PORIE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RV3028_CLKOUT_CLKSY BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RV3028_CLKOUT_CLKOE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RV3028_CTRL1_EERD BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RV3028_CTRL1_WADA BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RV3028_CTRL2_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RV3028_CTRL2_12_24 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RV3028_CTRL2_EIE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RV3028_CTRL2_AIE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RV3028_CTRL2_TIE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RV3028_CTRL2_UIE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RV3028_CTRL2_TSE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RV3028_EVT_CTRL_TSR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RV3028_EEPROM_CMD_UPDATE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RV3028_EEPROM_CMD_WRITE 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RV3028_EEPROM_CMD_READ 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RV3028_EEBUSY_POLL 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RV3028_EEBUSY_TIMEOUT 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RV3028_BACKUP_TCE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RV3028_BACKUP_TCR_MASK GENMASK(1,0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OFFSET_STEP_PPT 953674
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) enum rv3028_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) rv_3028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct rv3028_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) enum rv3028_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #ifdef CONFIG_COMMON_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct clk_hw clkout_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static u16 rv3028_trickle_resistors[] = {3000, 5000, 9000, 15000};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static ssize_t timestamp0_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct rv3028_data *rv3028 = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) regmap_update_bits(rv3028->regmap, RV3028_EVT_CTRL, RV3028_EVT_CTRL_TSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) RV3028_EVT_CTRL_TSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static ssize_t timestamp0_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct rv3028_data *rv3028 = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct rtc_time tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int ret, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u8 date[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ret = regmap_read(rv3028->regmap, RV3028_TS_COUNT, &count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (!count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ret = regmap_bulk_read(rv3028->regmap, RV3028_TS_SEC, date,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) sizeof(date));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) tm.tm_sec = bcd2bin(date[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) tm.tm_min = bcd2bin(date[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) tm.tm_hour = bcd2bin(date[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) tm.tm_mday = bcd2bin(date[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) tm.tm_mon = bcd2bin(date[4]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) tm.tm_year = bcd2bin(date[5]) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ret = rtc_valid_tm(&tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return sprintf(buf, "%llu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) (unsigned long long)rtc_tm_to_time64(&tm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static DEVICE_ATTR_RW(timestamp0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static ssize_t timestamp0_count_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct rv3028_data *rv3028 = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int ret, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = regmap_read(rv3028->regmap, RV3028_TS_COUNT, &count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return sprintf(buf, "%u\n", count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static DEVICE_ATTR_RO(timestamp0_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct attribute *rv3028_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) &dev_attr_timestamp0.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) &dev_attr_timestamp0_count.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const struct attribute_group rv3028_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .attrs = rv3028_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int rv3028_exit_eerd(struct rv3028_data *rv3028, u32 eerd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (eerd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return regmap_update_bits(rv3028->regmap, RV3028_CTRL1, RV3028_CTRL1_EERD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int rv3028_enter_eerd(struct rv3028_data *rv3028, u32 *eerd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 ctrl1, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ret = regmap_read(rv3028->regmap, RV3028_CTRL1, &ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) *eerd = ctrl1 & RV3028_CTRL1_EERD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (*eerd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) RV3028_CTRL1_EERD, RV3028_CTRL1_EERD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ret = regmap_read_poll_timeout(rv3028->regmap, RV3028_STATUS, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) !(status & RV3028_STATUS_EEBUSY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) RV3028_EEBUSY_POLL, RV3028_EEBUSY_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) rv3028_exit_eerd(rv3028, *eerd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int rv3028_update_eeprom(struct rv3028_data *rv3028, u32 eerd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ret = regmap_write(rv3028->regmap, RV3028_EEPROM_CMD, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) goto exit_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = regmap_write(rv3028->regmap, RV3028_EEPROM_CMD, RV3028_EEPROM_CMD_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) goto exit_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) usleep_range(63000, RV3028_EEBUSY_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ret = regmap_read_poll_timeout(rv3028->regmap, RV3028_STATUS, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) !(status & RV3028_STATUS_EEBUSY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) RV3028_EEBUSY_POLL, RV3028_EEBUSY_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) exit_eerd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) rv3028_exit_eerd(rv3028, eerd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int rv3028_update_cfg(struct rv3028_data *rv3028, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned int mask, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ret = rv3028_enter_eerd(rv3028, &eerd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = regmap_update_bits(rv3028->regmap, reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) rv3028_exit_eerd(rv3028, eerd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return rv3028_update_eeprom(rv3028, eerd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static irqreturn_t rv3028_handle_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct rv3028_data *rv3028 = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned long events = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 status = 0, ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (regmap_read(rv3028->regmap, RV3028_STATUS, &status) < 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) status == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (status & RV3028_STATUS_PORF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dev_warn(&rv3028->rtc->dev, "Voltage low, data loss detected.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (status & RV3028_STATUS_TF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) status |= RV3028_STATUS_TF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ctrl |= RV3028_CTRL2_TIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) events |= RTC_PF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (status & RV3028_STATUS_AF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) status |= RV3028_STATUS_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ctrl |= RV3028_CTRL2_AIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) events |= RTC_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (status & RV3028_STATUS_UF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) status |= RV3028_STATUS_UF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ctrl |= RV3028_CTRL2_UIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) events |= RTC_UF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (events) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) rtc_update_irq(rv3028->rtc, 1, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) regmap_update_bits(rv3028->regmap, RV3028_STATUS, status, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) regmap_update_bits(rv3028->regmap, RV3028_CTRL2, ctrl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (status & RV3028_STATUS_EVF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) sysfs_notify(&rv3028->rtc->dev.kobj, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_attr_timestamp0.attr.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dev_warn(&rv3028->rtc->dev, "event detected");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int rv3028_get_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct rv3028_data *rv3028 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u8 date[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int ret, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ret = regmap_read(rv3028->regmap, RV3028_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (status & RV3028_STATUS_PORF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dev_warn(dev, "Voltage low, data is invalid.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ret = regmap_bulk_read(rv3028->regmap, RV3028_SEC, date, sizeof(date));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) tm->tm_sec = bcd2bin(date[RV3028_SEC] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) tm->tm_min = bcd2bin(date[RV3028_MIN] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) tm->tm_hour = bcd2bin(date[RV3028_HOUR] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) tm->tm_wday = ilog2(date[RV3028_WDAY] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) tm->tm_mday = bcd2bin(date[RV3028_DAY] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) tm->tm_mon = bcd2bin(date[RV3028_MONTH] & 0x1f) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) tm->tm_year = bcd2bin(date[RV3028_YEAR]) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int rv3028_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct rv3028_data *rv3028 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u8 date[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) date[RV3028_SEC] = bin2bcd(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) date[RV3028_MIN] = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) date[RV3028_HOUR] = bin2bcd(tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) date[RV3028_WDAY] = 1 << (tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) date[RV3028_DAY] = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) date[RV3028_MONTH] = bin2bcd(tm->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) date[RV3028_YEAR] = bin2bcd(tm->tm_year - 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Writing to the Seconds register has the same effect as setting RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * bit to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ret = regmap_bulk_write(rv3028->regmap, RV3028_SEC, date,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) sizeof(date));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ret = regmap_update_bits(rv3028->regmap, RV3028_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) RV3028_STATUS_PORF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int rv3028_get_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct rv3028_data *rv3028 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u8 alarmvals[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int status, ctrl, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = regmap_bulk_read(rv3028->regmap, RV3028_ALARM_MIN, alarmvals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) sizeof(alarmvals));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ret = regmap_read(rv3028->regmap, RV3028_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ret = regmap_read(rv3028->regmap, RV3028_CTRL2, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) alrm->time.tm_sec = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) alrm->time.tm_min = bcd2bin(alarmvals[0] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) alrm->time.tm_hour = bcd2bin(alarmvals[1] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) alrm->time.tm_mday = bcd2bin(alarmvals[2] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) alrm->enabled = !!(ctrl & RV3028_CTRL2_AIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) alrm->pending = (status & RV3028_STATUS_AF) && alrm->enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static int rv3028_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct rv3028_data *rv3028 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u8 alarmvals[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u8 ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* The alarm has no seconds, round up to nearest minute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (alrm->time.tm_sec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) time64_t alarm_time = rtc_tm_to_time64(&alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) alarm_time += 60 - alrm->time.tm_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) rtc_time64_to_tm(alarm_time, &alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) RV3028_CTRL2_AIE | RV3028_CTRL2_UIE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) alarmvals[0] = bin2bcd(alrm->time.tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) alarmvals[1] = bin2bcd(alrm->time.tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) alarmvals[2] = bin2bcd(alrm->time.tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ret = regmap_update_bits(rv3028->regmap, RV3028_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) RV3028_STATUS_AF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ret = regmap_bulk_write(rv3028->regmap, RV3028_ALARM_MIN, alarmvals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) sizeof(alarmvals));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (alrm->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (rv3028->rtc->uie_rtctimer.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ctrl |= RV3028_CTRL2_UIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (rv3028->rtc->aie_timer.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ctrl |= RV3028_CTRL2_AIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) RV3028_CTRL2_UIE | RV3028_CTRL2_AIE, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int rv3028_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct rv3028_data *rv3028 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int ctrl = 0, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (rv3028->rtc->uie_rtctimer.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ctrl |= RV3028_CTRL2_UIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (rv3028->rtc->aie_timer.enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ctrl |= RV3028_CTRL2_AIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ret = regmap_update_bits(rv3028->regmap, RV3028_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) RV3028_STATUS_AF | RV3028_STATUS_UF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) RV3028_CTRL2_UIE | RV3028_CTRL2_AIE, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static int rv3028_read_offset(struct device *dev, long *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct rv3028_data *rv3028 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int ret, value, steps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = regmap_read(rv3028->regmap, RV3028_OFFSET, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) steps = sign_extend32(value << 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ret = regmap_read(rv3028->regmap, RV3028_BACKUP, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) steps += value >> 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) *offset = DIV_ROUND_CLOSEST(steps * OFFSET_STEP_PPT, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int rv3028_set_offset(struct device *dev, long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct rv3028_data *rv3028 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u32 eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) offset = clamp(offset, -244141L, 243187L) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) offset = DIV_ROUND_CLOSEST(offset, OFFSET_STEP_PPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ret = rv3028_enter_eerd(rv3028, &eerd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ret = regmap_write(rv3028->regmap, RV3028_OFFSET, offset >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) goto exit_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ret = regmap_update_bits(rv3028->regmap, RV3028_BACKUP, BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) offset << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) goto exit_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return rv3028_update_eeprom(rv3028, eerd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) exit_eerd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) rv3028_exit_eerd(rv3028, eerd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static int rv3028_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct rv3028_data *rv3028 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) int status, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) case RTC_VL_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ret = regmap_read(rv3028->regmap, RV3028_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) status = status & RV3028_STATUS_PORF ? RTC_VL_DATA_INVALID : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return put_user(status, (unsigned int __user *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static int rv3028_nvram_write(void *priv, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return regmap_bulk_write(priv, RV3028_RAM1 + offset, val, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int rv3028_nvram_read(void *priv, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return regmap_bulk_read(priv, RV3028_RAM1 + offset, val, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static int rv3028_eeprom_write(void *priv, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct rv3028_data *rv3028 = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u32 status, eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u8 *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ret = rv3028_enter_eerd(rv3028, &eerd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) for (i = 0; i < bytes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ret = regmap_write(rv3028->regmap, RV3028_EEPROM_ADDR, offset + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) goto restore_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ret = regmap_write(rv3028->regmap, RV3028_EEPROM_DATA, buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) goto restore_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ret = regmap_write(rv3028->regmap, RV3028_EEPROM_CMD, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) goto restore_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ret = regmap_write(rv3028->regmap, RV3028_EEPROM_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) RV3028_EEPROM_CMD_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) goto restore_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) usleep_range(RV3028_EEBUSY_POLL, RV3028_EEBUSY_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret = regmap_read_poll_timeout(rv3028->regmap, RV3028_STATUS, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) !(status & RV3028_STATUS_EEBUSY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) RV3028_EEBUSY_POLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) RV3028_EEBUSY_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) goto restore_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) restore_eerd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) rv3028_exit_eerd(rv3028, eerd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static int rv3028_eeprom_read(void *priv, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct rv3028_data *rv3028 = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) u32 status, eerd, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u8 *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ret = rv3028_enter_eerd(rv3028, &eerd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) for (i = 0; i < bytes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ret = regmap_write(rv3028->regmap, RV3028_EEPROM_ADDR, offset + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) goto restore_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ret = regmap_write(rv3028->regmap, RV3028_EEPROM_CMD, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) goto restore_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ret = regmap_write(rv3028->regmap, RV3028_EEPROM_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) RV3028_EEPROM_CMD_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) goto restore_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ret = regmap_read_poll_timeout(rv3028->regmap, RV3028_STATUS, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) !(status & RV3028_STATUS_EEBUSY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) RV3028_EEBUSY_POLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) RV3028_EEBUSY_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) goto restore_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ret = regmap_read(rv3028->regmap, RV3028_EEPROM_DATA, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) goto restore_eerd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) buf[i] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) restore_eerd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) rv3028_exit_eerd(rv3028, eerd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #ifdef CONFIG_COMMON_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define clkout_hw_to_rv3028(hw) container_of(hw, struct rv3028_data, clkout_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static int clkout_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 32768,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 8192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static unsigned long rv3028_clkout_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int clkout, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct rv3028_data *rv3028 = clkout_hw_to_rv3028(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ret = regmap_read(rv3028->regmap, RV3028_CLKOUT, &clkout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) clkout &= RV3028_CLKOUT_FD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return clkout_rates[clkout];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static long rv3028_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (clkout_rates[i] <= rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return clkout_rates[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static int rv3028_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) u32 enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct rv3028_data *rv3028 = clkout_hw_to_rv3028(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ret = regmap_read(rv3028->regmap, RV3028_CLKOUT, &enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ret = regmap_write(rv3028->regmap, RV3028_CLKOUT, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) enabled &= RV3028_CLKOUT_CLKOE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (clkout_rates[i] == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return rv3028_update_cfg(rv3028, RV3028_CLKOUT, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) RV3028_CLKOUT_CLKSY | enabled | i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static int rv3028_clkout_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct rv3028_data *rv3028 = clkout_hw_to_rv3028(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return regmap_write(rv3028->regmap, RV3028_CLKOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) RV3028_CLKOUT_CLKSY | RV3028_CLKOUT_CLKOE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static void rv3028_clkout_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct rv3028_data *rv3028 = clkout_hw_to_rv3028(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) regmap_write(rv3028->regmap, RV3028_CLKOUT, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) regmap_update_bits(rv3028->regmap, RV3028_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) RV3028_STATUS_CLKF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static int rv3028_clkout_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) int clkout, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct rv3028_data *rv3028 = clkout_hw_to_rv3028(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ret = regmap_read(rv3028->regmap, RV3028_CLKOUT, &clkout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return !!(clkout & RV3028_CLKOUT_CLKOE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static const struct clk_ops rv3028_clkout_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .prepare = rv3028_clkout_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .unprepare = rv3028_clkout_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .is_prepared = rv3028_clkout_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .recalc_rate = rv3028_clkout_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .round_rate = rv3028_clkout_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .set_rate = rv3028_clkout_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static int rv3028_clkout_register_clk(struct rv3028_data *rv3028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct device_node *node = client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ret = regmap_update_bits(rv3028->regmap, RV3028_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) RV3028_STATUS_CLKF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) init.name = "rv3028-clkout";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) init.ops = &rv3028_clkout_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) init.parent_names = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) init.num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) rv3028->clkout_hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* optional override of the clockname */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) of_property_read_string(node, "clock-output-names", &init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* register the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) clk = devm_clk_register(&client->dev, &rv3028->clkout_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (!IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) of_clk_add_provider(node, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static struct rtc_class_ops rv3028_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .read_time = rv3028_get_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .set_time = rv3028_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .read_offset = rv3028_read_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .set_offset = rv3028_set_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .ioctl = rv3028_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static const struct regmap_config regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .max_register = 0x37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static int rv3028_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct rv3028_data *rv3028;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) int ret, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) u32 ohms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct nvmem_config nvmem_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .name = "rv3028_nvram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .word_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .size = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .type = NVMEM_TYPE_BATTERY_BACKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .reg_read = rv3028_nvram_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .reg_write = rv3028_nvram_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct nvmem_config eeprom_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .name = "rv3028_eeprom",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .word_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .size = 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .type = NVMEM_TYPE_EEPROM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .reg_read = rv3028_eeprom_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .reg_write = rv3028_eeprom_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) rv3028 = devm_kzalloc(&client->dev, sizeof(struct rv3028_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (!rv3028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) rv3028->regmap = devm_regmap_init_i2c(client, ®map_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (IS_ERR(rv3028->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return PTR_ERR(rv3028->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) i2c_set_clientdata(client, rv3028);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) ret = regmap_read(rv3028->regmap, RV3028_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (status & RV3028_STATUS_PORF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) dev_warn(&client->dev, "Voltage low, data loss detected.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (status & RV3028_STATUS_AF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) dev_warn(&client->dev, "An alarm may have been missed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) rv3028->rtc = devm_rtc_allocate_device(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (IS_ERR(rv3028->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return PTR_ERR(rv3028->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (client->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ret = devm_request_threaded_irq(&client->dev, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) NULL, rv3028_handle_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) IRQF_TRIGGER_LOW | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) "rv3028", rv3028);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) client->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) rv3028_rtc_ops.read_alarm = rv3028_get_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) rv3028_rtc_ops.set_alarm = rv3028_set_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) rv3028_rtc_ops.alarm_irq_enable = rv3028_alarm_irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) RV3028_CTRL1_WADA, RV3028_CTRL1_WADA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* setup timestamping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) ret = regmap_update_bits(rv3028->regmap, RV3028_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) RV3028_CTRL2_EIE | RV3028_CTRL2_TSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) RV3028_CTRL2_EIE | RV3028_CTRL2_TSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* setup trickle charger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (!device_property_read_u32(&client->dev, "trickle-resistor-ohms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) &ohms)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) for (i = 0; i < ARRAY_SIZE(rv3028_trickle_resistors); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (ohms == rv3028_trickle_resistors[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (i < ARRAY_SIZE(rv3028_trickle_resistors)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ret = rv3028_update_cfg(rv3028, RV3028_BACKUP, RV3028_BACKUP_TCE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) RV3028_BACKUP_TCR_MASK, RV3028_BACKUP_TCE | i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) dev_warn(&client->dev, "invalid trickle resistor value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) ret = rtc_add_group(rv3028->rtc, &rv3028_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) rv3028->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) rv3028->rtc->range_max = RTC_TIMESTAMP_END_2099;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) rv3028->rtc->ops = &rv3028_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) ret = rtc_register_device(rv3028->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) nvmem_cfg.priv = rv3028->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) rtc_nvmem_register(rv3028->rtc, &nvmem_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) eeprom_cfg.priv = rv3028;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) rtc_nvmem_register(rv3028->rtc, &eeprom_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) rv3028->rtc->max_user_freq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #ifdef CONFIG_COMMON_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) rv3028_clkout_register_clk(rv3028, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static const struct of_device_id rv3028_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) { .compatible = "microcrystal,rv3028", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) MODULE_DEVICE_TABLE(of, rv3028_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static struct i2c_driver rv3028_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .name = "rtc-rv3028",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .of_match_table = of_match_ptr(rv3028_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .probe_new = rv3028_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) module_i2c_driver(rv3028_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@bootlin.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) MODULE_DESCRIPTION("Micro Crystal RV3028 RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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