^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * An I2C driver for Ricoh RS5C372, R2025S/D and RV5C38[67] RTCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005 Pavel Mironchik <pmironchik@optifacio.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2006 Tower Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2008 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Ricoh has a family of I2C based RTCs, which differ only slightly from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * each other. Differences center on pinout (e.g. how many interrupts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * output clock, etc) and how the control registers are used. The '372
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * is significant only because that's the one this driver first supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RS5C372_REG_SECS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RS5C372_REG_MINS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RS5C372_REG_HOURS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RS5C372_REG_WDAY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RS5C372_REG_DAY 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RS5C372_REG_MONTH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RS5C372_REG_YEAR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RS5C372_REG_TRIM 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) # define RS5C372_TRIM_XSL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) # define RS5C372_TRIM_MASK 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RS5C_REG_ALARM_A_MIN 8 /* or ALARM_W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RS5C_REG_ALARM_A_HOURS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RS5C_REG_ALARM_A_WDAY 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RS5C_REG_ALARM_B_MIN 11 /* or ALARM_D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RS5C_REG_ALARM_B_HOURS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RS5C_REG_ALARM_B_WDAY 13 /* (ALARM_B only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RS5C_REG_CTRL1 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) # define RS5C_CTRL1_AALE (1 << 7) /* or WALE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) # define RS5C_CTRL1_BALE (1 << 6) /* or DALE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) # define RV5C387_CTRL1_24 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) # define RS5C372A_CTRL1_SL1 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) # define RS5C_CTRL1_CT_MASK (7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) # define RS5C_CTRL1_CT0 (0 << 0) /* no periodic irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) # define RS5C_CTRL1_CT4 (4 << 0) /* 1 Hz level irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RS5C_REG_CTRL2 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) # define RS5C372_CTRL2_24 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) # define RS5C_CTRL2_XSTP (1 << 4) /* only if !R2x2x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) # define R2x2x_CTRL2_VDET (1 << 6) /* only if R2x2x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) # define R2x2x_CTRL2_XSTP (1 << 5) /* only if R2x2x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) # define R2x2x_CTRL2_PON (1 << 4) /* only if R2x2x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) # define RS5C_CTRL2_CTFG (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) # define RS5C_CTRL2_AAFG (1 << 1) /* or WAFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) # define RS5C_CTRL2_BAFG (1 << 0) /* or DAFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* to read (style 1) or write registers starting at R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RS5C_ADDR(R) (((R) << 4) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) enum rtc_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) rtc_undef = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) rtc_r2025sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) rtc_r2221tl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) rtc_rs5c372a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) rtc_rs5c372b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) rtc_rv5c386,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) rtc_rv5c387a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const struct i2c_device_id rs5c372_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { "r2025sd", rtc_r2025sd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { "r2221tl", rtc_r2221tl },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { "rs5c372a", rtc_rs5c372a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { "rs5c372b", rtc_rs5c372b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { "rv5c386", rtc_rv5c386 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { "rv5c387a", rtc_rv5c387a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MODULE_DEVICE_TABLE(i2c, rs5c372_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const struct of_device_id rs5c372_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .compatible = "ricoh,r2025sd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .data = (void *)rtc_r2025sd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .compatible = "ricoh,r2221tl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .data = (void *)rtc_r2221tl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .compatible = "ricoh,rs5c372a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .data = (void *)rtc_rs5c372a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .compatible = "ricoh,rs5c372b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .data = (void *)rtc_rs5c372b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .compatible = "ricoh,rv5c386",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .data = (void *)rtc_rv5c386
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .compatible = "ricoh,rv5c387a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .data = (void *)rtc_rv5c387a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MODULE_DEVICE_TABLE(of, rs5c372_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* REVISIT: this assumes that:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * - we're in the 21st century, so it's safe to ignore the century
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * bit for rv5c38[67] (REG_MONTH bit 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * - we should use ALARM_A not ALARM_B (may be wrong on some boards)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct rs5c372 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) enum rtc_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned time24:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned has_irq:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned smbus:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) char buf[17];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) char *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int rs5c_get_regs(struct rs5c372 *rs5c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct i2c_client *client = rs5c->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct i2c_msg msgs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .len = sizeof(rs5c->buf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .buf = rs5c->buf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* This implements the third reading method from the datasheet, using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * an internal address that's reset after each transaction (by STOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * to 0x0f ... so we read extra registers, and skip the first one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * The first method doesn't work with the iop3xx adapter driver, on at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * least 80219 chips; this works around that bug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * The third method on the other hand doesn't work for the SMBus-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * configurations, so we use the the first method there, stripping off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * the extra register in the process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (rs5c->smbus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int addr = RS5C_ADDR(RS5C372_REG_SECS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int size = sizeof(rs5c->buf) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (i2c_smbus_read_i2c_block_data(client, addr, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) rs5c->buf + 1) != size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dev_warn(&client->dev, "can't read registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if ((i2c_transfer(client->adapter, msgs, 1)) != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dev_warn(&client->dev, "can't read registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "%3ph (%02x) %3ph (%02x), %3ph, %3ph; %02x %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) rs5c->regs + 0, rs5c->regs[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) rs5c->regs + 4, rs5c->regs[7],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) rs5c->regs + 8, rs5c->regs + 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) rs5c->regs[14], rs5c->regs[15]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static unsigned rs5c_reg2hr(struct rs5c372 *rs5c, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (rs5c->time24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return bcd2bin(reg & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) hour = bcd2bin(reg & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (hour == 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) hour = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (reg & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) hour += 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static unsigned rs5c_hr2reg(struct rs5c372 *rs5c, unsigned hour)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (rs5c->time24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return bin2bcd(hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (hour > 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return 0x20 | bin2bcd(hour - 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (hour == 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return 0x20 | bin2bcd(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (hour == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return bin2bcd(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return bin2bcd(hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int rs5c372_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct rs5c372 *rs5c = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int status = rs5c_get_regs(rs5c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned char ctrl2 = rs5c->regs[RS5C_REG_CTRL2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) switch (rs5c->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) case rtc_r2025sd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) case rtc_r2221tl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if ((rs5c->type == rtc_r2025sd && !(ctrl2 & R2x2x_CTRL2_XSTP)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) (rs5c->type == rtc_r2221tl && (ctrl2 & R2x2x_CTRL2_XSTP))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dev_warn(&client->dev, "rtc oscillator interruption detected. Please reset the rtc clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (ctrl2 & RS5C_CTRL2_XSTP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_warn(&client->dev, "rtc oscillator interruption detected. Please reset the rtc clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) tm->tm_sec = bcd2bin(rs5c->regs[RS5C372_REG_SECS] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) tm->tm_min = bcd2bin(rs5c->regs[RS5C372_REG_MINS] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) tm->tm_hour = rs5c_reg2hr(rs5c, rs5c->regs[RS5C372_REG_HOURS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) tm->tm_wday = bcd2bin(rs5c->regs[RS5C372_REG_WDAY] & 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) tm->tm_mday = bcd2bin(rs5c->regs[RS5C372_REG_DAY] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* tm->tm_mon is zero-based */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) tm->tm_mon = bcd2bin(rs5c->regs[RS5C372_REG_MONTH] & 0x1f) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* year is 1900 + tm->tm_year */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) tm->tm_year = bcd2bin(rs5c->regs[RS5C372_REG_YEAR]) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "mday=%d, mon=%d, year=%d, wday=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) tm->tm_sec, tm->tm_min, tm->tm_hour,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int rs5c372_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct rs5c372 *rs5c = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned char buf[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned char ctrl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "mday=%d, mon=%d, year=%d, wday=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) tm->tm_sec, tm->tm_min, tm->tm_hour,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) addr = RS5C_ADDR(RS5C372_REG_SECS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) buf[0] = bin2bcd(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) buf[1] = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) buf[2] = rs5c_hr2reg(rs5c, tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) buf[3] = bin2bcd(tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) buf[4] = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) buf[5] = bin2bcd(tm->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) buf[6] = bin2bcd(tm->tm_year - 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (i2c_smbus_write_i2c_block_data(client, addr, sizeof(buf), buf) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dev_dbg(&client->dev, "%s: write error in line %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) addr = RS5C_ADDR(RS5C_REG_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ctrl2 = i2c_smbus_read_byte_data(client, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* clear rtc warning bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) switch (rs5c->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case rtc_r2025sd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case rtc_r2221tl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ctrl2 &= ~(R2x2x_CTRL2_VDET | R2x2x_CTRL2_PON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (rs5c->type == rtc_r2025sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ctrl2 |= R2x2x_CTRL2_XSTP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ctrl2 &= ~R2x2x_CTRL2_XSTP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ctrl2 &= ~RS5C_CTRL2_XSTP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (i2c_smbus_write_byte_data(client, addr, ctrl2) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dev_dbg(&client->dev, "%s: write error in line %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #if IS_ENABLED(CONFIG_RTC_INTF_PROC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define NEED_TRIM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #if IS_ENABLED(CONFIG_RTC_INTF_SYSFS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define NEED_TRIM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #ifdef NEED_TRIM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int rs5c372_get_trim(struct i2c_client *client, int *osc, int *trim)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct rs5c372 *rs5c372 = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u8 tmp = rs5c372->regs[RS5C372_REG_TRIM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (osc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) *osc = (tmp & RS5C372_TRIM_XSL) ? 32000 : 32768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (trim) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dev_dbg(&client->dev, "%s: raw trim=%x\n", __func__, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) tmp &= RS5C372_TRIM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (tmp & 0x3e) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int t = tmp & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (tmp & 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) t = (~t | (s8)0xc0) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) t = t - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) tmp = t * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) *trim = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int rs5c_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct rs5c372 *rs5c = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned char buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int status, addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) buf = rs5c->regs[RS5C_REG_CTRL1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (!rs5c->has_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) status = rs5c_get_regs(rs5c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) addr = RS5C_ADDR(RS5C_REG_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) buf |= RS5C_CTRL1_AALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) buf &= ~RS5C_CTRL1_AALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (i2c_smbus_write_byte_data(client, addr, buf) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dev_warn(dev, "can't update alarm\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) rs5c->regs[RS5C_REG_CTRL1] = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* NOTE: Since RTC_WKALM_{RD,SET} were originally defined for EFI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * which only exposes a polled programming interface; and since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * these calls map directly to those EFI requests; we don't demand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * we have an IRQ for this chip when we go through this API.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * The older x86_pc derived RTC_ALM_{READ,SET} calls require irqs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * though, managed through RTC_AIE_{ON,OFF} requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int rs5c_read_alarm(struct device *dev, struct rtc_wkalrm *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct rs5c372 *rs5c = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) status = rs5c_get_regs(rs5c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* report alarm time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) t->time.tm_sec = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) t->time.tm_min = bcd2bin(rs5c->regs[RS5C_REG_ALARM_A_MIN] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) t->time.tm_hour = rs5c_reg2hr(rs5c, rs5c->regs[RS5C_REG_ALARM_A_HOURS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* ... and status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) t->enabled = !!(rs5c->regs[RS5C_REG_CTRL1] & RS5C_CTRL1_AALE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) t->pending = !!(rs5c->regs[RS5C_REG_CTRL2] & RS5C_CTRL2_AAFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int rs5c_set_alarm(struct device *dev, struct rtc_wkalrm *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct rs5c372 *rs5c = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int status, addr, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) unsigned char buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* only handle up to 24 hours in the future, like RTC_ALM_SET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (t->time.tm_mday != -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) || t->time.tm_mon != -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) || t->time.tm_year != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* REVISIT: round up tm_sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* if needed, disable irq (clears pending status) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) status = rs5c_get_regs(rs5c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (rs5c->regs[RS5C_REG_CTRL1] & RS5C_CTRL1_AALE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) addr = RS5C_ADDR(RS5C_REG_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) buf[0] = rs5c->regs[RS5C_REG_CTRL1] & ~RS5C_CTRL1_AALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (i2c_smbus_write_byte_data(client, addr, buf[0]) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dev_dbg(dev, "can't disable alarm\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) rs5c->regs[RS5C_REG_CTRL1] = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* set alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) buf[0] = bin2bcd(t->time.tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) buf[1] = rs5c_hr2reg(rs5c, t->time.tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) buf[2] = 0x7f; /* any/all days */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) for (i = 0; i < sizeof(buf); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) addr = RS5C_ADDR(RS5C_REG_ALARM_A_MIN + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (i2c_smbus_write_byte_data(client, addr, buf[i]) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dev_dbg(dev, "can't set alarm time\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* ... and maybe enable its irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (t->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) addr = RS5C_ADDR(RS5C_REG_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) buf[0] = rs5c->regs[RS5C_REG_CTRL1] | RS5C_CTRL1_AALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (i2c_smbus_write_byte_data(client, addr, buf[0]) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_warn(dev, "can't enable alarm\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) rs5c->regs[RS5C_REG_CTRL1] = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #if IS_ENABLED(CONFIG_RTC_INTF_PROC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static int rs5c372_rtc_proc(struct device *dev, struct seq_file *seq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int err, osc, trim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) err = rs5c372_get_trim(to_i2c_client(dev), &osc, &trim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (err == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) seq_printf(seq, "crystal\t\t: %d.%03d KHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) osc / 1000, osc % 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) seq_printf(seq, "trim\t\t: %d\n", trim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define rs5c372_rtc_proc NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static const struct rtc_class_ops rs5c372_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .proc = rs5c372_rtc_proc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .read_time = rs5c372_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .set_time = rs5c372_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .read_alarm = rs5c_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .set_alarm = rs5c_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .alarm_irq_enable = rs5c_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #if IS_ENABLED(CONFIG_RTC_INTF_SYSFS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static ssize_t rs5c372_sysfs_show_trim(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) int err, trim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) err = rs5c372_get_trim(to_i2c_client(dev), NULL, &trim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return sprintf(buf, "%d\n", trim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static DEVICE_ATTR(trim, S_IRUGO, rs5c372_sysfs_show_trim, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static ssize_t rs5c372_sysfs_show_osc(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) int err, osc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) err = rs5c372_get_trim(to_i2c_client(dev), &osc, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return sprintf(buf, "%d.%03d KHz\n", osc / 1000, osc % 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static DEVICE_ATTR(osc, S_IRUGO, rs5c372_sysfs_show_osc, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static int rs5c_sysfs_register(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) err = device_create_file(dev, &dev_attr_trim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) err = device_create_file(dev, &dev_attr_osc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) device_remove_file(dev, &dev_attr_trim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static void rs5c_sysfs_unregister(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) device_remove_file(dev, &dev_attr_trim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) device_remove_file(dev, &dev_attr_osc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int rs5c_sysfs_register(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static void rs5c_sysfs_unregister(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #endif /* SYSFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static struct i2c_driver rs5c372_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static int rs5c_oscillator_setup(struct rs5c372 *rs5c372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) unsigned char buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) int addr, i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) addr = RS5C_ADDR(RS5C_REG_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) buf[0] = rs5c372->regs[RS5C_REG_CTRL1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) buf[1] = rs5c372->regs[RS5C_REG_CTRL2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) switch (rs5c372->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) case rtc_r2025sd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (buf[1] & R2x2x_CTRL2_XSTP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case rtc_r2221tl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (!(buf[1] & R2x2x_CTRL2_XSTP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (!(buf[1] & RS5C_CTRL2_XSTP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* use 24hr mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) switch (rs5c372->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) case rtc_rs5c372a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case rtc_rs5c372b:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) buf[1] |= RS5C372_CTRL2_24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) rs5c372->time24 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) case rtc_r2025sd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) case rtc_r2221tl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) case rtc_rv5c386:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) case rtc_rv5c387a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) buf[0] |= RV5C387_CTRL1_24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) rs5c372->time24 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* impossible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) for (i = 0; i < sizeof(buf); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) addr = RS5C_ADDR(RS5C_REG_CTRL1 + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ret = i2c_smbus_write_byte_data(rs5c372->client, addr, buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (unlikely(ret < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) rs5c372->regs[RS5C_REG_CTRL1] = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) rs5c372->regs[RS5C_REG_CTRL2] = buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static int rs5c372_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) int smbus_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct rs5c372 *rs5c372;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) dev_dbg(&client->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_I2C_BLOCK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * If we don't have any master mode adapter, try breaking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * it down in to the barest of capabilities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (i2c_check_functionality(client->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) I2C_FUNC_SMBUS_BYTE_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) I2C_FUNC_SMBUS_I2C_BLOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) smbus_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* Still no good, give up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) rs5c372 = devm_kzalloc(&client->dev, sizeof(struct rs5c372),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (!rs5c372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) rs5c372->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) i2c_set_clientdata(client, rs5c372);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (client->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) rs5c372->type = (enum rtc_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) of_device_get_match_data(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) rs5c372->type = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* we read registers 0x0f then 0x00-0x0f; skip the first one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) rs5c372->regs = &rs5c372->buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) rs5c372->smbus = smbus_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) err = rs5c_get_regs(rs5c372);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* clock may be set for am/pm or 24 hr time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) switch (rs5c372->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) case rtc_rs5c372a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) case rtc_rs5c372b:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* alarm uses ALARM_A; and nINTRA on 372a, nINTR on 372b.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * so does periodic irq, except some 327a modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (rs5c372->regs[RS5C_REG_CTRL2] & RS5C372_CTRL2_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) rs5c372->time24 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) case rtc_r2025sd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) case rtc_r2221tl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) case rtc_rv5c386:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) case rtc_rv5c387a:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (rs5c372->regs[RS5C_REG_CTRL1] & RV5C387_CTRL1_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) rs5c372->time24 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* alarm uses ALARM_W; and nINTRB for alarm and periodic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * irq, on both 386 and 387
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) dev_err(&client->dev, "unknown RTC type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* if the oscillator lost power and no other software (like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * the bootloader) set it up, do it here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * The R2025S/D does this a little differently than the other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * parts, so we special case that..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) err = rs5c_oscillator_setup(rs5c372);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (unlikely(err < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) dev_err(&client->dev, "setup error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dev_info(&client->dev, "%s found, %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ({ char *s; switch (rs5c372->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) case rtc_r2025sd: s = "r2025sd"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) case rtc_r2221tl: s = "r2221tl"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) case rtc_rs5c372a: s = "rs5c372a"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) case rtc_rs5c372b: s = "rs5c372b"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) case rtc_rv5c386: s = "rv5c386"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) case rtc_rv5c387a: s = "rv5c387a"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) default: s = "chip"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }; s;}),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) rs5c372->time24 ? "24hr" : "am/pm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* REVISIT use client->irq to register alarm irq ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) rs5c372->rtc = devm_rtc_device_register(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) rs5c372_driver.driver.name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) &rs5c372_rtc_ops, THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (IS_ERR(rs5c372->rtc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) err = PTR_ERR(rs5c372->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) err = rs5c_sysfs_register(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static int rs5c372_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) rs5c_sysfs_unregister(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static struct i2c_driver rs5c372_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .name = "rtc-rs5c372",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .of_match_table = of_match_ptr(rs5c372_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .probe = rs5c372_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .remove = rs5c372_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .id_table = rs5c372_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) module_i2c_driver(rs5c372_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) MODULE_AUTHOR(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) "Pavel Mironchik <pmironchik@optifacio.net>, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) "Alessandro Zummo <a.zummo@towertech.it>, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) "Paul Mundt <lethal@linux-sh.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) MODULE_DESCRIPTION("Ricoh RS5C372 RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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