^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * A SPI driver for the Ricoh RS5C348 RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006 Atsushi Nemoto <anemo@mba.ocn.ne.jp>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * The board specific init code should provide characteristics of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RS5C348_REG_SECS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RS5C348_REG_MINS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RS5C348_REG_HOURS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RS5C348_REG_WDAY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RS5C348_REG_DAY 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RS5C348_REG_MONTH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RS5C348_REG_YEAR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RS5C348_REG_CTL1 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RS5C348_REG_CTL2 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RS5C348_SECS_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RS5C348_MINS_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RS5C348_HOURS_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RS5C348_WDAY_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RS5C348_DAY_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RS5C348_MONTH_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RS5C348_BIT_PM 0x20 /* REG_HOURS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RS5C348_BIT_Y2K 0x80 /* REG_MONTH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RS5C348_BIT_24H 0x20 /* REG_CTL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RS5C348_BIT_XSTP 0x10 /* REG_CTL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RS5C348_BIT_VDET 0x40 /* REG_CTL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RS5C348_CMD_W(addr) (((addr) << 4) | 0x08) /* single write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RS5C348_CMD_R(addr) (((addr) << 4) | 0x0c) /* single read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RS5C348_CMD_MW(addr) (((addr) << 4) | 0x00) /* burst write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RS5C348_CMD_MR(addr) (((addr) << 4) | 0x04) /* burst read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct rs5c348_plat_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int rtc_24h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) rs5c348_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct rs5c348_plat_data *pdata = dev_get_platdata(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u8 txbuf[5+7], *txp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_CTL2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (ret & RS5C348_BIT_XSTP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) txbuf[0] = RS5C348_CMD_W(RS5C348_REG_CTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) txbuf[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ret = spi_write_then_read(spi, txbuf, 2, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Transfer 5 bytes before writing SEC. This gives 31us for carry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) txp = txbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) txbuf[1] = 0; /* dummy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) txbuf[3] = 0; /* dummy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) txbuf[4] = RS5C348_CMD_MW(RS5C348_REG_SECS); /* cmd, sec, ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) txp = &txbuf[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) txp[RS5C348_REG_SECS] = bin2bcd(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) txp[RS5C348_REG_MINS] = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (pdata->rtc_24h) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) txp[RS5C348_REG_HOURS] = bin2bcd(tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* hour 0 is AM12, noon is PM12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) txp[RS5C348_REG_HOURS] = bin2bcd((tm->tm_hour + 11) % 12 + 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) (tm->tm_hour >= 12 ? RS5C348_BIT_PM : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) txp[RS5C348_REG_WDAY] = bin2bcd(tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) txp[RS5C348_REG_DAY] = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) txp[RS5C348_REG_MONTH] = bin2bcd(tm->tm_mon + 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) (tm->tm_year >= 100 ? RS5C348_BIT_Y2K : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) txp[RS5C348_REG_YEAR] = bin2bcd(tm->tm_year % 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* write in one transfer to avoid data inconsistency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ret = spi_write_then_read(spi, txbuf, sizeof(txbuf), NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) udelay(62); /* Tcsr 62us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) rs5c348_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct rs5c348_plat_data *pdata = dev_get_platdata(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 txbuf[5], rxbuf[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_CTL2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (ret & RS5C348_BIT_VDET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dev_warn(&spi->dev, "voltage-low detected.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (ret & RS5C348_BIT_XSTP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dev_warn(&spi->dev, "oscillator-stop detected.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Transfer 5 byte befores reading SEC. This gives 31us for carry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) txbuf[1] = 0; /* dummy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) txbuf[3] = 0; /* dummy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) txbuf[4] = RS5C348_CMD_MR(RS5C348_REG_SECS); /* cmd, sec, ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* read in one transfer to avoid data inconsistency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ret = spi_write_then_read(spi, txbuf, sizeof(txbuf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) rxbuf, sizeof(rxbuf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) udelay(62); /* Tcsr 62us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) tm->tm_sec = bcd2bin(rxbuf[RS5C348_REG_SECS] & RS5C348_SECS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) tm->tm_min = bcd2bin(rxbuf[RS5C348_REG_MINS] & RS5C348_MINS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) tm->tm_hour = bcd2bin(rxbuf[RS5C348_REG_HOURS] & RS5C348_HOURS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (!pdata->rtc_24h) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (rxbuf[RS5C348_REG_HOURS] & RS5C348_BIT_PM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) tm->tm_hour -= 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) tm->tm_hour %= 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) tm->tm_hour += 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) tm->tm_hour %= 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) tm->tm_wday = bcd2bin(rxbuf[RS5C348_REG_WDAY] & RS5C348_WDAY_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) tm->tm_mday = bcd2bin(rxbuf[RS5C348_REG_DAY] & RS5C348_DAY_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) tm->tm_mon =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) bcd2bin(rxbuf[RS5C348_REG_MONTH] & RS5C348_MONTH_MASK) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* year is 1900 + tm->tm_year */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) tm->tm_year = bcd2bin(rxbuf[RS5C348_REG_YEAR]) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ((rxbuf[RS5C348_REG_MONTH] & RS5C348_BIT_Y2K) ? 100 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const struct rtc_class_ops rs5c348_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .read_time = rs5c348_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .set_time = rs5c348_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int rs5c348_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct rs5c348_plat_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) pdata = devm_kzalloc(&spi->dev, sizeof(struct rs5c348_plat_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) spi->dev.platform_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Check D7 of SECOND register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_SECS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (ret < 0 || (ret & 0x80)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dev_err(&spi->dev, "not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dev_info(&spi->dev, "spiclk %u KHz.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) (spi->max_speed_hz + 500) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_CTL1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (ret & RS5C348_BIT_24H)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) pdata->rtc_24h = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) rtc = devm_rtc_allocate_device(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (IS_ERR(rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return PTR_ERR(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pdata->rtc = rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) rtc->ops = &rs5c348_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return rtc_register_device(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static struct spi_driver rs5c348_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .name = "rtc-rs5c348",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .probe = rs5c348_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) module_spi_driver(rs5c348_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MODULE_DESCRIPTION("Ricoh RS5C348 RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MODULE_ALIAS("spi:rtc-rs5c348");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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