^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Ricoh RS5C313 RTC device/driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2007 Nobuhiro Iwamatsu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * 2005-09-19 modifed by kogiidena
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on the old drivers/char/rs5c313_rtc.c by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Based on code written by Paul Gortmaker.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 1996 Paul Gortmaker
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Based on other minimal char device drivers, like Alan's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * watchdog, Ted's random, etc. etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * 1.07 Paul Gortmaker.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * 1.08 Miquel van Smoorenburg: disallow certain things on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * DEC Alpha as the CMOS clock is also used for other things.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * 1.09 Nikita Schmidt: epoch support and some Alpha cleanup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * 1.09a Pete Zaitcev: Sun SPARC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * 1.09b Jeff Garzik: Modularize, init cleanup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * 1.09c Jeff Garzik: SMP cleanup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * 1.10 Paul Barton-Davis: add support for async I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 1.10a Andrea Arcangeli: Alpha updates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * 1.10b Andrew Morton: SMP lock fix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * 1.10c Cesar Barros: SMP locking fixes and cleanup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * 1.10d Paul Gortmaker: delete paranoia check in rtc_exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * 1.10e Maciej W. Rozycki: Handle DECstation's year weirdness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * 1.11 Takashi Iwai: Kernel access functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * rtc_register/rtc_unregister/rtc_control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * 1.11a Daniele Bellucci: Audit create_proc_read_entry in rtc_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * 1.12 Venkatesh Pallipadi: Hooks for emulating rtc on HPET base-timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * CONFIG_HPET_EMULATE_RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * 1.13 Nobuhiro Iwamatsu: Updata driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DRV_NAME "rs5c313"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #ifdef CONFIG_SH_LANDISK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*****************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* LANDISK dependence part of RS5C313 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*****************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SCSMR1 0xFFE00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SCSCR1 0xFFE00008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SCSMR1_CA 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SCSCR1_CKE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SCSPTR1 0xFFE0001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SCSPTR1_EIO 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SCSPTR1_SPB1IO 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SCSPTR1_SPB1DT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SCSPTR1_SPB0IO 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SCSPTR1_SPB0DT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SDA_OEN SCSPTR1_SPB1IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SDA SCSPTR1_SPB1DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SCL_OEN SCSPTR1_SPB0IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SCL SCSPTR1_SPB0DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* RICOH RS5C313 CE port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RS5C313_CE 0xB0000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* RICOH RS5C313 CE port bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RS5C313_CE_RTCCE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* SCSPTR1 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned char scsptr1_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RS5C313_CEENABLE __raw_writeb(RS5C313_CE_RTCCE, RS5C313_CE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RS5C313_CEDISABLE __raw_writeb(0x00, RS5C313_CE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RS5C313_MISCOP __raw_writeb(0x02, 0xB0000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void rs5c313_init_port(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Set SCK as I/O port and Initialize SCSPTR1 data & I/O port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __raw_writeb(__raw_readb(SCSMR1) & ~SCSMR1_CA, SCSMR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __raw_writeb(__raw_readb(SCSCR1) & ~SCSCR1_CKE, SCSCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* And Initialize SCL for RS5C313 clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) scsptr1_data = __raw_readb(SCSPTR1) | SCL; /* SCL:H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __raw_writeb(scsptr1_data, SCSPTR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) scsptr1_data = __raw_readb(SCSPTR1) | SCL_OEN; /* SCL output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) __raw_writeb(scsptr1_data, SCSPTR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) RS5C313_CEDISABLE; /* CE:L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void rs5c313_write_data(unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* SDA:Write Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) scsptr1_data = (scsptr1_data & ~SDA) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ((((0x80 >> i) & data) >> (7 - i)) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) __raw_writeb(scsptr1_data, SCSPTR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) scsptr1_data |= SDA_OEN; /* SDA:output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) __raw_writeb(scsptr1_data, SCSPTR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ndelay(700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) scsptr1_data &= ~SCL; /* SCL:L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __raw_writeb(scsptr1_data, SCSPTR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ndelay(700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) scsptr1_data |= SCL; /* SCL:H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) __raw_writeb(scsptr1_data, SCSPTR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) scsptr1_data &= ~SDA_OEN; /* SDA:output disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __raw_writeb(scsptr1_data, SCSPTR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static unsigned char rs5c313_read_data(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned char data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ndelay(700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* SDA:Read Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) data |= ((__raw_readb(SCSPTR1) & SDA) >> 2) << (7 - i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) scsptr1_data &= ~SCL; /* SCL:L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) __raw_writeb(scsptr1_data, SCSPTR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ndelay(700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) scsptr1_data |= SCL; /* SCL:H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) __raw_writeb(scsptr1_data, SCSPTR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return data & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #endif /* CONFIG_SH_LANDISK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*****************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* machine independence part of RS5C313 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*****************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* RICOH RS5C313 address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define RS5C313_ADDR_SEC 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define RS5C313_ADDR_SEC10 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define RS5C313_ADDR_MIN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define RS5C313_ADDR_MIN10 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define RS5C313_ADDR_HOUR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define RS5C313_ADDR_HOUR10 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define RS5C313_ADDR_WEEK 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define RS5C313_ADDR_INTINTVREG 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define RS5C313_ADDR_DAY 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define RS5C313_ADDR_DAY10 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define RS5C313_ADDR_MON 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define RS5C313_ADDR_MON10 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define RS5C313_ADDR_YEAR 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define RS5C313_ADDR_YEAR10 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define RS5C313_ADDR_CNTREG 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define RS5C313_ADDR_TESTREG 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* RICOH RS5C313 control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define RS5C313_CNTREG_ADJ_BSY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define RS5C313_CNTREG_WTEN_XSTP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define RS5C313_CNTREG_12_24 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define RS5C313_CNTREG_CTFG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* RICOH RS5C313 test register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define RS5C313_TESTREG_TEST 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* RICOH RS5C313 control bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define RS5C313_CNTBIT_READ 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define RS5C313_CNTBIT_AD 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define RS5C313_CNTBIT_DT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static unsigned char rs5c313_read_reg(unsigned char addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) rs5c313_write_data(addr | RS5C313_CNTBIT_READ | RS5C313_CNTBIT_AD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return rs5c313_read_data();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static void rs5c313_write_reg(unsigned char addr, unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) data &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) rs5c313_write_data(addr | RS5C313_CNTBIT_AD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) rs5c313_write_data(data | RS5C313_CNTBIT_DT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static inline unsigned char rs5c313_read_cntreg(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return rs5c313_read_reg(RS5C313_ADDR_CNTREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static inline void rs5c313_write_cntreg(unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) rs5c313_write_reg(RS5C313_ADDR_CNTREG, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static inline void rs5c313_write_intintvreg(unsigned char data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) rs5c313_write_reg(RS5C313_ADDR_INTINTVREG, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int rs5c313_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) RS5C313_CEENABLE; /* CE:H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Initialize control reg. 24 hour */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) rs5c313_write_cntreg(0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) RS5C313_CEDISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ndelay(700); /* CE:L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (cnt++ > 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_err(dev, "%s: timeout error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) data = rs5c313_read_reg(RS5C313_ADDR_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) data |= (rs5c313_read_reg(RS5C313_ADDR_SEC10) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) tm->tm_sec = bcd2bin(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) data = rs5c313_read_reg(RS5C313_ADDR_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) data |= (rs5c313_read_reg(RS5C313_ADDR_MIN10) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) tm->tm_min = bcd2bin(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) data = rs5c313_read_reg(RS5C313_ADDR_HOUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) data |= (rs5c313_read_reg(RS5C313_ADDR_HOUR10) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) tm->tm_hour = bcd2bin(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) data = rs5c313_read_reg(RS5C313_ADDR_DAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) data |= (rs5c313_read_reg(RS5C313_ADDR_DAY10) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) tm->tm_mday = bcd2bin(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) data = rs5c313_read_reg(RS5C313_ADDR_MON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) data |= (rs5c313_read_reg(RS5C313_ADDR_MON10) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) tm->tm_mon = bcd2bin(data) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) data = rs5c313_read_reg(RS5C313_ADDR_YEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) data |= (rs5c313_read_reg(RS5C313_ADDR_YEAR10) << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) tm->tm_year = bcd2bin(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (tm->tm_year < 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) tm->tm_year += 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) data = rs5c313_read_reg(RS5C313_ADDR_WEEK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) tm->tm_wday = bcd2bin(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) RS5C313_CEDISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ndelay(700); /* CE:L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int rs5c313_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* busy check. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) RS5C313_CEENABLE; /* CE:H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Initiatlize control reg. 24 hour */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) rs5c313_write_cntreg(0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) RS5C313_MISCOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) RS5C313_CEDISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ndelay(700); /* CE:L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (cnt++ > 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev_err(dev, "%s: timeout error\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) data = bin2bcd(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) rs5c313_write_reg(RS5C313_ADDR_SEC, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) rs5c313_write_reg(RS5C313_ADDR_SEC10, (data >> 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) data = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) rs5c313_write_reg(RS5C313_ADDR_MIN, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) rs5c313_write_reg(RS5C313_ADDR_MIN10, (data >> 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) data = bin2bcd(tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) rs5c313_write_reg(RS5C313_ADDR_HOUR, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) rs5c313_write_reg(RS5C313_ADDR_HOUR10, (data >> 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) data = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) rs5c313_write_reg(RS5C313_ADDR_DAY, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) rs5c313_write_reg(RS5C313_ADDR_DAY10, (data >> 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) data = bin2bcd(tm->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) rs5c313_write_reg(RS5C313_ADDR_MON, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) rs5c313_write_reg(RS5C313_ADDR_MON10, (data >> 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) data = bin2bcd(tm->tm_year % 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) rs5c313_write_reg(RS5C313_ADDR_YEAR, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) rs5c313_write_reg(RS5C313_ADDR_YEAR10, (data >> 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) data = bin2bcd(tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) rs5c313_write_reg(RS5C313_ADDR_WEEK, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) RS5C313_CEDISABLE; /* CE:H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ndelay(700);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static void rs5c313_check_xstp_bit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct rtc_time tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) RS5C313_CEENABLE; /* CE:H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (rs5c313_read_cntreg() & RS5C313_CNTREG_WTEN_XSTP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* INT interval reg. OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) rs5c313_write_intintvreg(0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Initialize control reg. 24 hour & adjust */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) rs5c313_write_cntreg(0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* busy check. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) for (cnt = 0; cnt < 100; cnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (!(rs5c313_read_cntreg() & RS5C313_CNTREG_ADJ_BSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) RS5C313_MISCOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) memset(&tm, 0, sizeof(struct rtc_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) tm.tm_mday = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) tm.tm_mon = 1 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) tm.tm_year = 2000 - 1900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) rs5c313_rtc_set_time(NULL, &tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) pr_err("invalid value, resetting to 1 Jan 2000\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) RS5C313_CEDISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ndelay(700); /* CE:L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static const struct rtc_class_ops rs5c313_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .read_time = rs5c313_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .set_time = rs5c313_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int rs5c313_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) rs5c313_init_port();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) rs5c313_check_xstp_bit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) rtc = devm_rtc_device_register(&pdev->dev, "rs5c313", &rs5c313_rtc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return PTR_ERR_OR_ZERO(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static struct platform_driver rs5c313_rtc_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .probe = rs5c313_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) module_platform_driver(rs5c313_rtc_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) MODULE_AUTHOR("kogiidena , Nobuhiro Iwamatsu <iwamatsu@nigauri.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MODULE_DESCRIPTION("Ricoh RS5C313 RTC device driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MODULE_ALIAS("platform:" DRV_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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