^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Ricoh RP5C01 RTC Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2009 Geert Uytterhoeven
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on the A3000 TOD code in arch/m68k/amiga/config.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 1993 Hamish Macdonald
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) RP5C01_1_SECOND = 0x0, /* MODE 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) RP5C01_10_SECOND = 0x1, /* MODE 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) RP5C01_1_MINUTE = 0x2, /* MODE 00 and MODE 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) RP5C01_10_MINUTE = 0x3, /* MODE 00 and MODE 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) RP5C01_1_HOUR = 0x4, /* MODE 00 and MODE 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) RP5C01_10_HOUR = 0x5, /* MODE 00 and MODE 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) RP5C01_DAY_OF_WEEK = 0x6, /* MODE 00 and MODE 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) RP5C01_1_DAY = 0x7, /* MODE 00 and MODE 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) RP5C01_10_DAY = 0x8, /* MODE 00 and MODE 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) RP5C01_1_MONTH = 0x9, /* MODE 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) RP5C01_10_MONTH = 0xa, /* MODE 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) RP5C01_1_YEAR = 0xb, /* MODE 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) RP5C01_10_YEAR = 0xc, /* MODE 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) RP5C01_12_24_SELECT = 0xa, /* MODE 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) RP5C01_LEAP_YEAR = 0xb, /* MODE 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) RP5C01_MODE = 0xd, /* all modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) RP5C01_TEST = 0xe, /* all modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) RP5C01_RESET = 0xf, /* all modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RP5C01_12_24_SELECT_12 (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RP5C01_12_24_SELECT_24 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RP5C01_10_HOUR_AM (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RP5C01_10_HOUR_PM (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RP5C01_MODE_TIMER_EN (1 << 3) /* timer enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RP5C01_MODE_ALARM_EN (1 << 2) /* alarm enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RP5C01_MODE_MODE_MASK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RP5C01_MODE_MODE00 (0 << 0) /* time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RP5C01_MODE_MODE01 (1 << 0) /* alarm, 12h/24h, leap year */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RP5C01_MODE_RAM_BLOCK10 (2 << 0) /* RAM 4 bits x 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RP5C01_MODE_RAM_BLOCK11 (3 << 0) /* RAM 4 bits x 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RP5C01_RESET_1HZ_PULSE (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RP5C01_RESET_16HZ_PULSE (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RP5C01_RESET_SECOND (1 << 1) /* reset divider stages for */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* seconds or smaller units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RP5C01_RESET_ALARM (1 << 0) /* reset all alarm registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct rp5c01_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) spinlock_t lock; /* against concurrent RTC/NVRAM access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static inline unsigned int rp5c01_read(struct rp5c01_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return __raw_readl(&priv->regs[reg]) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static inline void rp5c01_write(struct rp5c01_priv *priv, unsigned int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __raw_writel(val, &priv->regs[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void rp5c01_lock(struct rp5c01_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) rp5c01_write(priv, RP5C01_MODE_MODE00, RP5C01_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void rp5c01_unlock(struct rp5c01_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) rp5c01_write(priv, RP5C01_MODE_TIMER_EN | RP5C01_MODE_MODE01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) RP5C01_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int rp5c01_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct rp5c01_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) spin_lock_irq(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) rp5c01_lock(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) tm->tm_sec = rp5c01_read(priv, RP5C01_10_SECOND) * 10 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) rp5c01_read(priv, RP5C01_1_SECOND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) tm->tm_min = rp5c01_read(priv, RP5C01_10_MINUTE) * 10 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) rp5c01_read(priv, RP5C01_1_MINUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) tm->tm_hour = rp5c01_read(priv, RP5C01_10_HOUR) * 10 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) rp5c01_read(priv, RP5C01_1_HOUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) tm->tm_mday = rp5c01_read(priv, RP5C01_10_DAY) * 10 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) rp5c01_read(priv, RP5C01_1_DAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) tm->tm_wday = rp5c01_read(priv, RP5C01_DAY_OF_WEEK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) tm->tm_mon = rp5c01_read(priv, RP5C01_10_MONTH) * 10 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) rp5c01_read(priv, RP5C01_1_MONTH) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) tm->tm_year = rp5c01_read(priv, RP5C01_10_YEAR) * 10 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) rp5c01_read(priv, RP5C01_1_YEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (tm->tm_year <= 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) tm->tm_year += 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) rp5c01_unlock(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) spin_unlock_irq(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int rp5c01_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct rp5c01_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) spin_lock_irq(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) rp5c01_lock(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) rp5c01_write(priv, tm->tm_sec / 10, RP5C01_10_SECOND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) rp5c01_write(priv, tm->tm_sec % 10, RP5C01_1_SECOND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) rp5c01_write(priv, tm->tm_min / 10, RP5C01_10_MINUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) rp5c01_write(priv, tm->tm_min % 10, RP5C01_1_MINUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) rp5c01_write(priv, tm->tm_hour / 10, RP5C01_10_HOUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) rp5c01_write(priv, tm->tm_hour % 10, RP5C01_1_HOUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) rp5c01_write(priv, tm->tm_mday / 10, RP5C01_10_DAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) rp5c01_write(priv, tm->tm_mday % 10, RP5C01_1_DAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (tm->tm_wday != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) rp5c01_write(priv, tm->tm_wday, RP5C01_DAY_OF_WEEK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) rp5c01_write(priv, (tm->tm_mon + 1) / 10, RP5C01_10_MONTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) rp5c01_write(priv, (tm->tm_mon + 1) % 10, RP5C01_1_MONTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (tm->tm_year >= 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) tm->tm_year -= 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) rp5c01_write(priv, tm->tm_year / 10, RP5C01_10_YEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) rp5c01_write(priv, tm->tm_year % 10, RP5C01_1_YEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) rp5c01_unlock(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) spin_unlock_irq(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct rtc_class_ops rp5c01_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .read_time = rp5c01_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .set_time = rp5c01_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * The NVRAM is organized as 2 blocks of 13 nibbles of 4 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * We provide access to them like AmigaOS does: the high nibble of each 8-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * byte is stored in BLOCK10, the low nibble in BLOCK11.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int rp5c01_nvram_read(void *_priv, unsigned int pos, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct rp5c01_priv *priv = _priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u8 *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) spin_lock_irq(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) for (; bytes; bytes--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) rp5c01_write(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) RP5C01_MODE_TIMER_EN | RP5C01_MODE_RAM_BLOCK10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) RP5C01_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) data = rp5c01_read(priv, pos) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) rp5c01_write(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) RP5C01_MODE_TIMER_EN | RP5C01_MODE_RAM_BLOCK11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) RP5C01_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) data |= rp5c01_read(priv, pos++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) rp5c01_write(priv, RP5C01_MODE_TIMER_EN | RP5C01_MODE_MODE01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) RP5C01_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) *buf++ = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) spin_unlock_irq(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int rp5c01_nvram_write(void *_priv, unsigned int pos, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct rp5c01_priv *priv = _priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u8 *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) spin_lock_irq(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) for (; bytes; bytes--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 data = *buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) rp5c01_write(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) RP5C01_MODE_TIMER_EN | RP5C01_MODE_RAM_BLOCK10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) RP5C01_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) rp5c01_write(priv, data >> 4, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) rp5c01_write(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) RP5C01_MODE_TIMER_EN | RP5C01_MODE_RAM_BLOCK11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) RP5C01_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) rp5c01_write(priv, data & 0xf, pos++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) rp5c01_write(priv, RP5C01_MODE_TIMER_EN | RP5C01_MODE_MODE01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) RP5C01_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) spin_unlock_irq(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int __init rp5c01_rtc_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct rp5c01_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct nvmem_config nvmem_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .name = "rp5c01_nvram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .word_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .size = RP5C01_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .reg_read = rp5c01_nvram_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .reg_write = rp5c01_nvram_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) res = platform_get_resource(dev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) priv->regs = devm_ioremap(&dev->dev, res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (!priv->regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) spin_lock_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) platform_set_drvdata(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) rtc = devm_rtc_allocate_device(&dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (IS_ERR(rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return PTR_ERR(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) rtc->ops = &rp5c01_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) rtc->nvram_old_abi = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) priv->rtc = rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) nvmem_cfg.priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) error = rtc_nvmem_register(rtc, &nvmem_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return rtc_register_device(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static struct platform_driver rp5c01_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .name = "rtc-rp5c01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) module_platform_driver_probe(rp5c01_rtc_driver, rp5c01_rtc_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MODULE_AUTHOR("Geert Uytterhoeven <geert@linux-m68k.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MODULE_DESCRIPTION("Ricoh RP5C01 RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MODULE_ALIAS("platform:rtc-rp5c01");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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