^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2022 Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* RTC_CTRL_REG bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RTC_REG(x) ((x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RTC_SET_SECONDS RTC_REG(0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RTC_SET_MINUTES RTC_REG(0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RTC_SET_HOURS RTC_REG(0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RTC_SET_DAYS RTC_REG(0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RTC_SET_MONTHS RTC_REG(0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RTC_SET_YEARL RTC_REG(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RTC_SET_YEARH RTC_REG(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RTC_SET_WEEKS RTC_REG(0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RTC_ALARM_SECONDS RTC_REG(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RTC_ALARM_MINUTES RTC_REG(0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RTC_ALARM_HOURS RTC_REG(0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RTC_ALARM_DAYS RTC_REG(0x2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RTC_ALARM_MONTHS RTC_REG(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RTC_ALARM_YEARL RTC_REG(0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RTC_ALARM_YEARH RTC_REG(0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RTC_CTRL RTC_REG(0x3C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RTC_STATUS0 RTC_REG(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RTC_STATUS1 RTC_REG(0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RTC_INT0_EN RTC_REG(0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RTC_INT1_EN RTC_REG(0x4c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RTC_MSEC_CTRL RTC_REG(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RTC_MSEC_CNT RTC_REG(0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RTC_COMP_H RTC_REG(0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RTC_COMP_D RTC_REG(0x5c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RTC_COMP_M RTC_REG(0x60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RTC_ANALOG_CTRL RTC_REG(0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RTC_ANALOG_TEST RTC_REG(0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RTC_LDO_CTRL RTC_REG(0x6c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RTC_XO_TRIM0 RTC_REG(0x70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RTC_XO_TRIM1 RTC_REG(0x74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RTC_VPTAT_TRIM RTC_REG(0x78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RTC_ANALOG_EN RTC_REG(0x7c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RTC_CLK32K_TEST RTC_REG(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RTC_TEST_ST RTC_REG(0x84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RTC_TEST_LEN RTC_REG(0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RTC_CNT_0 RTC_REG(0x8c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RTC_CNT_1 RTC_REG(0x90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RTC_CNT_2 RTC_REG(0x94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RTC_CNT_3 RTC_REG(0x98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RTC_MAX_REGISTER RTC_CNT_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define VI_GRF_VI_MISC_CON0 0x50000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RTC_CLAMP_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* RTC_CTRL_REG bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RTC_CTRL_REG_START_RTC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* RK630 has a shadowed register for saving a "frozen" RTC time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * When user setting "GET_TIME" to 1, the time will save in this shadowed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * register. If set "READSEL" to 1, user read rtc time register, actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * get the time of that moment. If we need the real time, clr this bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RTC_CTRL_REG_RTC_GET_TIME BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RTC_CTRL_REG_RTC_READSEL_M BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RTC_INT_REG_ALARM_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RTC_D2A_XO_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RTC_D2A_CLK_OUT_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RTC_STATUS_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SECONDS_REG_MSK 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MINUTES_REG_MAK 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HOURS_REG_MSK 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DAYS_REG_MSK 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MONTHS_REG_MSK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define YEARS_REG_MSK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define WEEKS_REG_MSK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RTC_VREF_INIT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define D2A_POR_REG_SEL1 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define D2A_POR_REG_SEL0 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define NUM_TIME_REGS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define NUM_ALARM_REGS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DISABLE_ALARM_INT 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ENABLE_ALARM_INT 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ALARM_INT_STATUS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CLK32K_TEST_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK32K_TEST_START BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK32K_TEST_STATUS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK32K_TEST_DONE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK32K_TEST_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK32K_COMP_DIR_ADD BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK32K_COMP_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK32K_NO_COMP 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK32K_TEST_REF_CLK 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RTC_WRITE_MASK 0xc4522900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ROCKCHIP_RV1106_RTC = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct rockchip_rtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct regmap *grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct clk_bulk_data *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static unsigned int rockchip_rtc_write(struct regmap *map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return regmap_write(map, offset, val | RTC_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static unsigned int rockchip_rtc_update_bits(struct regmap *map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 offset, u32 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) regmap_read(map, offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return regmap_write(map, offset, (val & ~mask) | set | RTC_WRITE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Read current time and date in RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int rockchip_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct rockchip_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 rtc_data[NUM_TIME_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int yearl, yearh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* No shadowed registers, need read time three time to update time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ret = regmap_bulk_read(rtc->regmap, RTC_SET_SECONDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) rtc_data, NUM_TIME_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dev_err(dev, "Failed to bulk read rtc_data: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ret = regmap_bulk_read(rtc->regmap, RTC_SET_SECONDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) rtc_data, NUM_TIME_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dev_err(dev, "Failed to bulk read rtc_data: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ret = regmap_bulk_read(rtc->regmap, RTC_SET_SECONDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) rtc_data, NUM_TIME_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) dev_err(dev, "Failed to bulk read rtc_data: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) tm->tm_sec = bcd2bin(rtc_data[0] & SECONDS_REG_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) tm->tm_min = bcd2bin(rtc_data[1] & MINUTES_REG_MAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) tm->tm_hour = bcd2bin(rtc_data[2] & HOURS_REG_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) tm->tm_mday = bcd2bin(rtc_data[3] & DAYS_REG_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) tm->tm_mon = (bcd2bin(rtc_data[4] & MONTHS_REG_MSK)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) yearl = (bcd2bin(rtc_data[5] & YEARS_REG_MSK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) yearh = (bcd2bin(rtc_data[6] & YEARS_REG_MSK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) tm->tm_year = yearh * 100 + yearl + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) tm->tm_wday = bcd2bin(rtc_data[7] & WEEKS_REG_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dev_dbg(dev, "RTC date/time %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Set current time and date in RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int rockchip_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct rockchip_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 rtc_data[NUM_TIME_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int ret, status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int yearl, yearh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) dev_dbg(dev, "set RTC date/time %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) rtc_data[0] = bin2bcd(tm->tm_sec) | RTC_WRITE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) rtc_data[1] = bin2bcd(tm->tm_min) | RTC_WRITE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) rtc_data[2] = bin2bcd(tm->tm_hour) | RTC_WRITE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) rtc_data[3] = bin2bcd(tm->tm_mday) | RTC_WRITE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) rtc_data[4] = bin2bcd(tm->tm_mon + 1) | RTC_WRITE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (tm->tm_year > 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) yearh = (tm->tm_year - 100) / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) yearl = tm->tm_year - 100 - yearh * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) yearh = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) yearl = tm->tm_year - 100 - yearh * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) rtc_data[5] = bin2bcd(yearl) | RTC_WRITE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) rtc_data[6] = bin2bcd(yearh) | RTC_WRITE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) rtc_data[7] = bin2bcd(tm->tm_wday) | RTC_WRITE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Stop RTC while updating the RTC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ret = rockchip_rtc_update_bits(rtc->regmap, RTC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) RTC_CTRL_REG_START_RTC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dev_err(dev, "Failed to update RTC control: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret = regmap_read(rtc->regmap, RTC_STATUS1, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) while (status & RTC_CTRL_REG_START_RTC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ret = regmap_read(rtc->regmap, RTC_STATUS1, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_err(dev, "Failed to read RTC_STATUS1: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ret = regmap_bulk_write(rtc->regmap, RTC_SET_SECONDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) rtc_data, NUM_TIME_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_err(dev, "Failed to bull write rtc_data: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Start RTC again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ret = rockchip_rtc_update_bits(rtc->regmap, RTC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) RTC_CTRL_REG_RTC_READSEL_M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) RTC_CTRL_REG_START_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) RTC_CTRL_REG_RTC_READSEL_M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) RTC_CTRL_REG_START_RTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dev_err(dev, "Failed to update RTC control: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ret = regmap_read(rtc->regmap, RTC_STATUS1, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) while (!(status & RTC_CTRL_REG_START_RTC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ret = regmap_read(rtc->regmap, RTC_STATUS1, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev_err(dev, "Failed to read RTC_STATUS1: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Read alarm time and date in RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int rockchip_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct rockchip_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 alrm_data[NUM_ALARM_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 int_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int yearl, yearh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ret = regmap_bulk_read(rtc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) RTC_ALARM_SECONDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) alrm_data, NUM_ALARM_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dev_err(dev, "Failed to read RTC alarm date REG: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) alrm->time.tm_sec = bcd2bin(alrm_data[0] & SECONDS_REG_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) alrm->time.tm_min = bcd2bin(alrm_data[1] & MINUTES_REG_MAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) alrm->time.tm_hour = bcd2bin(alrm_data[2] & HOURS_REG_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) alrm->time.tm_mday = bcd2bin(alrm_data[3] & DAYS_REG_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) alrm->time.tm_mon = (bcd2bin(alrm_data[4] & MONTHS_REG_MSK)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) yearl = (bcd2bin(alrm_data[5] & YEARS_REG_MSK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) yearh = (bcd2bin(alrm_data[6] & YEARS_REG_MSK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) alrm->time.tm_year = yearh * 100 + yearl + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = regmap_read(rtc->regmap, RTC_INT0_EN, &int_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dev_err(dev, "Failed to read RTC INT REG: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) "alrm read RTC date/time %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 1900 + alrm->time.tm_year, alrm->time.tm_mon + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) alrm->time.tm_mday, alrm->time.tm_wday, alrm->time.tm_hour,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) alrm->time.tm_min, alrm->time.tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) alrm->enabled = (int_reg & RTC_INT_REG_ALARM_EN) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int rockchip_rtc_stop_alarm(struct rockchip_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ret = rockchip_rtc_write(rtc->regmap, RTC_INT0_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int rockchip_rtc_start_alarm(struct rockchip_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ret = rockchip_rtc_write(rtc->regmap, RTC_STATUS0, RTC_STATUS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret = rockchip_rtc_write(rtc->regmap, RTC_STATUS0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ret = rockchip_rtc_write(rtc->regmap, RTC_INT0_EN, ENABLE_ALARM_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int rockchip_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct rockchip_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 alrm_data[NUM_ALARM_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int yearl, yearh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = rockchip_rtc_stop_alarm(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dev_err(dev, "Failed to stop alarm: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "alrm set RTC date/time %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 1900 + alrm->time.tm_year, alrm->time.tm_mon + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) alrm->time.tm_mday, alrm->time.tm_wday, alrm->time.tm_hour,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) alrm->time.tm_min, alrm->time.tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) alrm_data[0] = bin2bcd(alrm->time.tm_sec) | RTC_WRITE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) alrm_data[1] = bin2bcd(alrm->time.tm_min) | RTC_WRITE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) alrm_data[2] = bin2bcd(alrm->time.tm_hour) | RTC_WRITE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) alrm_data[3] = bin2bcd(alrm->time.tm_mday) | RTC_WRITE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) alrm_data[4] = bin2bcd(alrm->time.tm_mon + 1) | RTC_WRITE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (alrm->time.tm_year > 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) yearh = (alrm->time.tm_year - 100) / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) yearl = alrm->time.tm_year - 100 - yearh * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) yearh = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) yearl = alrm->time.tm_year - 100 - yearh * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) alrm_data[5] = bin2bcd(yearl) | RTC_WRITE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) alrm_data[6] = bin2bcd(yearh) | RTC_WRITE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ret = regmap_bulk_write(rtc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) RTC_ALARM_SECONDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) alrm_data, NUM_ALARM_REGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dev_err(dev, "Failed to bulk write: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (alrm->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ret = rockchip_rtc_start_alarm(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dev_err(dev, "Failed to start alarm: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int rockchip_rtc_alarm_irq_enable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct rockchip_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return rockchip_rtc_start_alarm(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return rockchip_rtc_stop_alarm(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * We will just handle setting the frequency and make use the framework for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * reading the periodic interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static irqreturn_t rockchip_rtc_alarm_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct rockchip_rtc *rtc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int ret, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ret = regmap_read(rtc->regmap, RTC_STATUS0, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pr_err("Failed to read RTC INT REG: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ret = rockchip_rtc_write(rtc->regmap, RTC_STATUS0, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) pr_err("%s:Failed to update RTC status: %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (status & ALARM_INT_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) pr_info("Alarm by: %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static const struct rtc_class_ops rockchip_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .read_time = rockchip_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .set_time = rockchip_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .read_alarm = rockchip_rtc_readalarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .set_alarm = rockchip_rtc_setalarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .alarm_irq_enable = rockchip_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * Due to the analog generator 32k clock affected by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * temperature, voltage, clock precision need test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * with the environment change. In rtc test,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * use 24M clock as reference clock to measure the 32k clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * Before start test 32k clock, we should enable clk32k test(0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * and configure test length, when rtc test done(0x84[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * latch the 24M clock domain counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * and read out the counter from rtc_test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * registers(0x8c~0x98) via apb bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * In RTC digital design, we set three level compensation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * the compensation value due to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * RTC 32k clock test result, and if we need compensation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * we need configure the compensation enable bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * Comp every hour, compensation at last minute every hour,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * and support add time and sub time by the MSB bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * Comp every day, compensation at last minute in last hour every day,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * and support add time and sub time by the MSB bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * Comp every month, compensation at last minute
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * in last hour in last day every month,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * and support add time and sub time by the MSB bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int rockchip_rtc_compensation(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct rockchip_rtc *rtc = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u64 camp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) u32 count[4], counts, g_ref, tcamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) int ret, done = 0, trim_dir, c_hour,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) c_day, c_det_day, c_mon, c_det_mon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ret = rockchip_rtc_update_bits(rtc->regmap, RTC_CLK32K_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) CLK32K_TEST_EN, CLK32K_TEST_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) "%s:Failed to update RTC CLK32K TEST: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = rockchip_rtc_write(rtc->regmap, RTC_TEST_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) CLK32K_TEST_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) "%s:Failed to update RTC CLK32K TEST LEN: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ret = rockchip_rtc_update_bits(rtc->regmap, RTC_TEST_ST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) CLK32K_TEST_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) CLK32K_TEST_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) "%s:Failed to update RTC CLK32K TEST STATUS : %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ret = regmap_read_poll_timeout(rtc->regmap, RTC_TEST_ST, done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) (done & CLK32K_TEST_DONE), 0, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "%s:timeout waiting for RTC TEST STATUS : %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ret = regmap_bulk_read(rtc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) RTC_CNT_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) count, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dev_err(dev, "Failed to read RTC count REG: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) counts = count[0] | (count[1] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) (count[2] << 16) | (count[3] << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) g_ref = CLK32K_TEST_REF_CLK * (CLK32K_TEST_LEN + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (counts > g_ref) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) trim_dir = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) camp = 36ULL * (32768 * (counts - g_ref));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) do_div(camp, (g_ref / 100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) trim_dir = CLK32K_COMP_DIR_ADD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) camp = 36ULL * (32768 * (g_ref - counts));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) do_div(camp, (g_ref / 100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) tcamp = (u32)camp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) c_hour = DIV_ROUND_CLOSEST(tcamp, 32768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) c_day = DIV_ROUND_CLOSEST(24 * tcamp, 32768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) c_mon = DIV_ROUND_CLOSEST(30 * 24 * tcamp, 32768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (c_hour > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) rockchip_rtc_write(rtc->regmap, RTC_COMP_H, (c_hour - 1) | trim_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) rockchip_rtc_write(rtc->regmap, RTC_COMP_H, CLK32K_NO_COMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (c_day > c_hour * 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) c_det_day = c_day - c_hour * 23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) trim_dir = CLK32K_COMP_DIR_ADD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) c_det_day = c_hour * 24 - c_day;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) trim_dir = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (c_det_day > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) rockchip_rtc_write(rtc->regmap, RTC_COMP_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) (c_det_day - 1) | trim_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) rockchip_rtc_write(rtc->regmap, RTC_COMP_D, CLK32K_NO_COMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (c_mon > (29 * c_day + 23 * c_hour)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) c_det_mon = c_mon - 29 * c_day - 23 * c_hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) trim_dir = CLK32K_COMP_DIR_ADD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) c_det_mon = 29 * c_day + 23 * c_hour - c_mon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) trim_dir = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (c_det_mon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) rockchip_rtc_write(rtc->regmap, RTC_COMP_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) (c_det_mon - 1) | trim_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) rockchip_rtc_write(rtc->regmap, RTC_COMP_M, CLK32K_NO_COMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ret = regmap_read(rtc->regmap, RTC_CTRL, &done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev_err(dev, "Failed to read RTC_CTRL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ret = rockchip_rtc_update_bits(rtc->regmap, RTC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) CLK32K_COMP_EN, CLK32K_COMP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) "%s:Failed to update RTC CTRL : %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* Enable the alarm if it should be enabled (in case it was disabled to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * prevent use as a wake source).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* Turn off the alarm if it should not be a wake source. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static int rockchip_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct rockchip_rtc *rtc = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) enable_irq_wake(rtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (rtc->grf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) switch (rtc->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case ROCKCHIP_RV1106_RTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) regmap_write(rtc->grf, VI_GRF_VI_MISC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) (RTC_CLAMP_EN << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) clk_bulk_disable_unprepare(rtc->num_clks, rtc->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* Enable the alarm if it should be enabled (in case it was disabled to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * prevent use as a wake source).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static int rockchip_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct rockchip_rtc *rtc = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) disable_irq_wake(rtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (rtc->grf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) switch (rtc->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) case ROCKCHIP_RV1106_RTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) regmap_write(rtc->grf, VI_GRF_VI_MISC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) (RTC_CLAMP_EN << 16) | RTC_CLAMP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ret = clk_bulk_prepare_enable(rtc->num_clks, rtc->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dev_err(dev, "Cannot enable clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static SIMPLE_DEV_PM_OPS(rockchip_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) rockchip_rtc_suspend, rockchip_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static const struct of_device_id rockchip_rtc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .compatible = "rockchip,rv1106-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .data = (void *)ROCKCHIP_RV1106_RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) MODULE_DEVICE_TABLE(of, rockchip_rtc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static void rockchip_rtc_clk_disable(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct rockchip_rtc *rtc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) clk_bulk_disable_unprepare(rtc->num_clks, rtc->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static int rockchip_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct rockchip_rtc *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct rtc_time tm_read, tm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .tm_wday = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .tm_year = 121,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .tm_mon = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .tm_mday = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .tm_hour = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .tm_min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .tm_sec = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (!rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) rtc->regmap = device_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (IS_ERR(rtc->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return dev_err_probe(dev, PTR_ERR(rtc->regmap),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) "no regmap available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) rtc->mode = (unsigned int)of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) rtc->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (IS_ERR(rtc->grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) dev_warn(dev, "Missing rockchip,grf property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) rtc->grf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) switch (rtc->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) case ROCKCHIP_RV1106_RTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) regmap_write(rtc->grf, VI_GRF_VI_MISC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) (RTC_CLAMP_EN << 16) | RTC_CLAMP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) platform_set_drvdata(pdev, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) rtc->num_clks = devm_clk_bulk_get_all(&pdev->dev, &rtc->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (rtc->num_clks < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ret = clk_bulk_prepare_enable(rtc->num_clks, rtc->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return dev_err_probe(dev, ret, "Cannot enable clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ret = devm_add_action_or_reset(dev, rockchip_rtc_clk_disable, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return dev_err_probe(dev, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) "Failed to add clk disable action.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ret = rockchip_rtc_update_bits(rtc->regmap, RTC_VPTAT_TRIM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) D2A_POR_REG_SEL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) D2A_POR_REG_SEL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return dev_err_probe(&pdev->dev, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) "Failed to write RTC_VPTAT_TRIM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ret = rockchip_rtc_update_bits(rtc->regmap, RTC_ANALOG_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) D2A_POR_REG_SEL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return dev_err_probe(&pdev->dev, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) "Failed to write RTC_ANALOG_EN\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ret = rockchip_rtc_update_bits(rtc->regmap, RTC_LDO_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) RTC_D2A_XO_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) RTC_D2A_XO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return dev_err_probe(&pdev->dev, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) "Failed to update RTC_LDO_CTRL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ret = rockchip_rtc_update_bits(rtc->regmap, RTC_ANALOG_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) RTC_D2A_CLK_OUT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) RTC_D2A_CLK_OUT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return dev_err_probe(&pdev->dev, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) "Failed to update RTC_ANALOG_EN\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) rockchip_rtc_compensation(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* start rtc running by default, and use shadowed timer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ret = rockchip_rtc_update_bits(rtc->regmap, RTC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) RTC_CTRL_REG_START_RTC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) RTC_CTRL_REG_RTC_READSEL_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) RTC_CTRL_REG_RTC_READSEL_M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) RTC_CTRL_REG_START_RTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return dev_err_probe(&pdev->dev, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) "Failed to update RTC control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ret = rockchip_rtc_write(rtc->regmap, RTC_STATUS0, RTC_STATUS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return dev_err_probe(&pdev->dev, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) "Failed to write RTC status0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ret = rockchip_rtc_write(rtc->regmap, RTC_STATUS0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return dev_err_probe(&pdev->dev, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) "Failed to write RTC status0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) rockchip_rtc_read_time(&pdev->dev, &tm_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (rtc_valid_tm(&tm_read) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) rockchip_rtc_set_time(&pdev->dev, &tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (IS_ERR(rtc->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return PTR_ERR(rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) rtc->rtc->ops = &rockchip_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) rtc->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (rtc->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return dev_err_probe(&pdev->dev, rtc->irq, "No IRQ resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* request alarm irq of rtc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ret = devm_request_threaded_irq(&pdev->dev, rtc->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) &rockchip_rtc_alarm_irq, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) "RTC alarm", rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return dev_err_probe(&pdev->dev, ret,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) "Failed to request alarm IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) rtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return rtc_register_device(rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static struct platform_driver rockchip_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .probe = rockchip_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .name = "rockchip-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .pm = &rockchip_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .of_match_table = rockchip_rtc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) module_platform_driver(rockchip_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) MODULE_DESCRIPTION("RTC driver for the rockchip");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) MODULE_AUTHOR("Zhang Qing <zhangqing@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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