^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018, Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Jeffy Chen <jeffy.chen@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Base on the Rockchip timer driver drivers/clocksource/rockchip_timer.c by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Daniel Lezcano <daniel.lezcano@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DRV_NAME "rk-timer-rtc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TIMER_LOAD_COUNT0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TIMER_LOAD_COUNT1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TIMER_CURRENT_VALUE0 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TIMER_CURRENT_VALUE1 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TIMER_CONTROL_REG3288 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TIMER_INT_STATUS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TIMER_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TIMER_MODE_USER_DEFINED_COUNT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TIMER_INT_UNMASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Forbid any alarms which would trigger inside the threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TIMER_ALARM_THRESHOLD_MS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #if !defined(UINT64_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define UINT64_MAX ((u64)-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * struct rk_timer_rtc_data - Differences between SoC variants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @ctrl_reg_offset: The offset of timer control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct rk_timer_rtc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int ctrl_reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * struct rk_timer_rtc - Driver data for Rockchip timer RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @data: Pointer to rk_timer_rtc_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @regmap: Register map of the timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @rtc: Pointer to RTC device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @clk: The timer clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @pclk: The peripheral clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @freq: The freq of timer clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @timebase: The base time of the timer RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @alarm_irq_enabled: Whether to report alarm irqs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @irq: The timer IRQ number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct rk_timer_rtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) const struct rk_timer_rtc_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u64 timebase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int alarm_irq_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static inline u64 tick_to_sec(struct rk_timer_rtc *rk_timer_rtc, u64 tick)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) do_div(tick, rk_timer_rtc->freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return tick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static inline u64 ms_to_tick(struct rk_timer_rtc *rk_timer_rtc, int ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return ms * rk_timer_rtc->freq / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static inline u64 tick_to_time64(struct rk_timer_rtc *rk_timer_rtc, u64 tick)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return tick_to_sec(rk_timer_rtc, tick) + rk_timer_rtc->timebase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static inline u64 time64_to_tick(struct rk_timer_rtc *rk_timer_rtc, u64 time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return (time - rk_timer_rtc->timebase) * rk_timer_rtc->freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static inline int rk_timer_rtc_write64(struct rk_timer_rtc *rk_timer_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 reg, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return regmap_bulk_write(rk_timer_rtc->regmap, reg, &val, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static inline int rk_timer_rtc_read64(struct rk_timer_rtc *rk_timer_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 reg, u64 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 val_lo, val_hi, tmp_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ret = regmap_read(rk_timer_rtc->regmap, reg + 4, &val_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ret = regmap_read(rk_timer_rtc->regmap, reg, &val_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ret = regmap_read(rk_timer_rtc->regmap, reg + 4, &tmp_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) } while (val_hi != tmp_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) *val = ((u64) val_hi << 32) | val_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline int rk_timer_rtc_irq_clear(struct rk_timer_rtc *rk_timer_rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return regmap_write(rk_timer_rtc->regmap, TIMER_INT_STATUS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static inline int rk_timer_rtc_irq_enable(struct rk_timer_rtc *rk_timer_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Clear any pending irq before enable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) rk_timer_rtc_irq_clear(rk_timer_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return regmap_update_bits(rk_timer_rtc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) rk_timer_rtc->data->ctrl_reg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) TIMER_INT_UNMASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) enabled ? TIMER_INT_UNMASK : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int rk_timer_rtc_reset(struct rk_timer_rtc *rk_timer_rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ret = regmap_write(rk_timer_rtc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) rk_timer_rtc->data->ctrl_reg_offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Init load count to UINT64_MAX to keep timer running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ret = rk_timer_rtc_write64(rk_timer_rtc, TIMER_LOAD_COUNT0, UINT64_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Clear any pending irq before enable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) rk_timer_rtc_irq_clear(rk_timer_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Enable timer in user-defined count mode with irq unmasked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return regmap_write(rk_timer_rtc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) rk_timer_rtc->data->ctrl_reg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) TIMER_ENABLE | TIMER_MODE_USER_DEFINED_COUNT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) TIMER_INT_UNMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int rk_timer_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct rk_timer_rtc *rk_timer_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u64 tick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = rk_timer_rtc_read64(rk_timer_rtc, TIMER_CURRENT_VALUE0, &tick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) rtc_time64_to_tm(tick_to_time64(rk_timer_rtc, tick), tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dev_dbg(dev, "Read RTC: %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return rtc_valid_tm(tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int rk_timer_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct rk_timer_rtc *rk_timer_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dev_dbg(dev, "Set RTC:%4d-%02d-%02d(%d) %02d:%02d:%02d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 1900 + tm->tm_year, tm->tm_mon + 1, tm->tm_mday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) tm->tm_wday, tm->tm_hour, tm->tm_min, tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = rtc_valid_tm(tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) rk_timer_rtc->timebase = rtc_tm_to_time64(tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_dbg(dev, "Setting new timebase:%lld\n", rk_timer_rtc->timebase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Restart timer for new timebase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ret = rk_timer_rtc_reset(rk_timer_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dev_err(dev, "Failed to reset timer:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Tell framework to check alarms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) rtc_update_irq(rk_timer_rtc->rtc, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int rk_timer_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct rk_timer_rtc *rk_timer_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u64 tick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = rk_timer_rtc_read64(rk_timer_rtc, TIMER_LOAD_COUNT0, &tick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) rtc_time64_to_tm(tick_to_time64(rk_timer_rtc, tick), &alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev_dbg(dev, "Read alarm: %4d-%02d-%02d(%d) %02d:%02d:%02d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 1900 + alrm->time.tm_year, alrm->time.tm_mon + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) alrm->time.tm_mday, alrm->time.tm_wday, alrm->time.tm_hour,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) alrm->time.tm_min, alrm->time.tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return rtc_valid_tm(&alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int rk_timer_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct rk_timer_rtc *rk_timer_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u64 alarm_tick, alarm_threshold_tick, cur_tick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev_dbg(dev, "Set alarm:%4d-%02d-%02d(%d) %02d:%02d:%02d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 1900 + alrm->time.tm_year, alrm->time.tm_mon + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) alrm->time.tm_mday, alrm->time.tm_wday, alrm->time.tm_hour,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) alrm->time.tm_min, alrm->time.tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ret = rtc_valid_tm(&alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) rk_timer_rtc->alarm_irq_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) alarm_tick = time64_to_tick(rk_timer_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) rtc_tm_to_time64(&alrm->time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ret = rk_timer_rtc_read64(rk_timer_rtc, TIMER_CURRENT_VALUE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) &cur_tick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Don't set an alarm in the past or about to pass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) alarm_threshold_tick = ms_to_tick(rk_timer_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) TIMER_ALARM_THRESHOLD_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (alarm_tick <= (cur_tick + alarm_threshold_tick))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return -ETIME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * When the current value counts up to the load count, the timer will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * stop and generate an irq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ret = rk_timer_rtc_write64(rk_timer_rtc, TIMER_LOAD_COUNT0, alarm_tick);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev_dbg(dev, "New alarm enabled:%d\n", alrm->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) rk_timer_rtc->alarm_irq_enabled = alrm->enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int rk_timer_rtc_alarm_irq_enable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct rk_timer_rtc *rk_timer_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dev_dbg(dev, "Set alarm irq enabled:%d\n", enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) rk_timer_rtc->alarm_irq_enabled = enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static irqreturn_t rk_timer_rtc_alarm_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct device *dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct rk_timer_rtc *rk_timer_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) dev_dbg(dev, "Received timer irq, alarm_irq_enabled:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) rk_timer_rtc->alarm_irq_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* The timer is stopped now, reset the load count to start it again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ret = rk_timer_rtc_write64(rk_timer_rtc, TIMER_LOAD_COUNT0, UINT64_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dev_err(dev, "Failed to set load count:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ret = regmap_write(rk_timer_rtc->regmap, TIMER_INT_STATUS, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dev_err(dev, "Failed to clear irq:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Only report rtc irq when alarm irq is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (rk_timer_rtc->alarm_irq_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) rtc_update_irq(rk_timer_rtc->rtc, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static const struct rtc_class_ops rk_timer_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .read_time = rk_timer_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .set_time = rk_timer_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .read_alarm = rk_timer_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .set_alarm = rk_timer_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .alarm_irq_enable = rk_timer_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static struct regmap_config rk_timer_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const struct of_device_id rk_timer_rtc_dt_match[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int rk_timer_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct rk_timer_rtc *rk_timer_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) resource_size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) rk_timer_rtc = devm_kzalloc(dev, sizeof(*rk_timer_rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (!rk_timer_rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) match = of_match_node(rk_timer_rtc_dt_match, dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) rk_timer_rtc->data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) platform_set_drvdata(pdev, rk_timer_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) base = devm_of_iomap(dev, dev->of_node, 0, &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dev_err(dev, "Failed to iomap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) rk_timer_regmap_config.max_register = size - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) rk_timer_rtc->regmap = devm_regmap_init_mmio(dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) &rk_timer_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (IS_ERR(rk_timer_rtc->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ret = PTR_ERR(rk_timer_rtc->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dev_err(dev, "Failed to init regmap:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) rk_timer_rtc->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (rk_timer_rtc->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = rk_timer_rtc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dev_err(dev, "Failed to get irq:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ret = devm_request_irq(dev, rk_timer_rtc->irq, rk_timer_rtc_alarm_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 0, dev_name(dev), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dev_err(dev, "Failed to request irq:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) rk_timer_rtc->pclk = devm_clk_get(dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (IS_ERR(rk_timer_rtc->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ret = PTR_ERR(rk_timer_rtc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) pr_err("Failed to get timer pclk:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ret = clk_prepare_enable(rk_timer_rtc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_err(dev, "Failed to enable pclk:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) rk_timer_rtc->clk = devm_clk_get(dev, "timer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (IS_ERR(rk_timer_rtc->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ret = PTR_ERR(rk_timer_rtc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) pr_err("Failed to get timer clk:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) goto err_disable_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ret = clk_prepare_enable(rk_timer_rtc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dev_err(dev, "Failed to enable timer clk:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) goto err_disable_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) rk_timer_rtc->freq = clk_get_rate(rk_timer_rtc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dev_dbg(dev, "RTC timer freq:%d\n", rk_timer_rtc->freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ret = rk_timer_rtc_reset(rk_timer_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dev_err(dev, "Failed to reset timer:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ret = device_init_wakeup(dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dev_err(dev, "Failed to init wakeup:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) goto err_disable_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) rk_timer_rtc->rtc = devm_rtc_device_register(dev, DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) &rk_timer_rtc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (IS_ERR(rk_timer_rtc->rtc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ret = PTR_ERR(rk_timer_rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev_err(dev, "Failed to register rtc:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) goto err_uninit_wakeup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) err_uninit_wakeup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) device_init_wakeup(&pdev->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) err_disable_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) rk_timer_rtc_irq_enable(rk_timer_rtc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) err_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) clk_disable_unprepare(rk_timer_rtc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) err_disable_pclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) clk_disable_unprepare(rk_timer_rtc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int rk_timer_rtc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct rk_timer_rtc *rk_timer_rtc = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) device_init_wakeup(&pdev->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) rk_timer_rtc_irq_enable(rk_timer_rtc, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) clk_disable_unprepare(rk_timer_rtc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) clk_disable_unprepare(rk_timer_rtc->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int rk_timer_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct rk_timer_rtc *rk_timer_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) enable_irq_wake(rk_timer_rtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int rk_timer_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct rk_timer_rtc *rk_timer_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) disable_irq_wake(rk_timer_rtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static SIMPLE_DEV_PM_OPS(rk_timer_rtc_pm_ops, rk_timer_rtc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) rk_timer_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static const struct rk_timer_rtc_data rk3288_timer_rtc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .ctrl_reg_offset = TIMER_CONTROL_REG3288,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static const struct of_device_id rk_timer_rtc_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .compatible = "rockchip,rk3308-timer-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .data = &rk3288_timer_rtc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) MODULE_DEVICE_TABLE(platform, rk_timer_rtc_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static struct platform_driver rk_timer_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .probe = rk_timer_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .remove = rk_timer_rtc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .pm = &rk_timer_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .of_match_table = of_match_ptr(rk_timer_rtc_dt_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) module_platform_driver(rk_timer_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) MODULE_DESCRIPTION("RTC driver for the rockchip timer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) MODULE_AUTHOR("Jeffy Chen <jeffy.chen@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) MODULE_ALIAS("platform:" DRV_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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