^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * EPSON TOYOCOM RTC-7301SF/DG Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 Akinobu Mita <akinobu.mita@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on rtc-rp5c01.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Datasheet: http://www5.epsondevice.com/en/products/parallel/rtc7301sf.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DRV_NAME "rtc-r7301"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RTC7301_1_SEC 0x0 /* Bank 0 and Band 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RTC7301_10_SEC 0x1 /* Bank 0 and Band 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RTC7301_AE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RTC7301_1_MIN 0x2 /* Bank 0 and Band 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RTC7301_10_MIN 0x3 /* Bank 0 and Band 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RTC7301_1_HOUR 0x4 /* Bank 0 and Band 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RTC7301_10_HOUR 0x5 /* Bank 0 and Band 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RTC7301_DAY_OF_WEEK 0x6 /* Bank 0 and Band 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RTC7301_1_DAY 0x7 /* Bank 0 and Band 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RTC7301_10_DAY 0x8 /* Bank 0 and Band 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RTC7301_1_MONTH 0x9 /* Bank 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RTC7301_10_MONTH 0xa /* Bank 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RTC7301_1_YEAR 0xb /* Bank 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RTC7301_10_YEAR 0xc /* Bank 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RTC7301_100_YEAR 0xd /* Bank 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RTC7301_1000_YEAR 0xe /* Bank 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RTC7301_ALARM_CONTROL 0xe /* Bank 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RTC7301_ALARM_CONTROL_AIE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RTC7301_ALARM_CONTROL_AF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RTC7301_TIMER_CONTROL 0xe /* Bank 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RTC7301_TIMER_CONTROL_TIE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RTC7301_TIMER_CONTROL_TF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RTC7301_CONTROL 0xf /* All banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RTC7301_CONTROL_BUSY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RTC7301_CONTROL_STOP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RTC7301_CONTROL_BANK_SEL_0 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RTC7301_CONTROL_BANK_SEL_1 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct rtc7301_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u8 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const struct regmap_config rtc7301_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static u8 rtc7301_read(struct rtc7301_priv *priv, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int reg_stride = regmap_get_reg_stride(priv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) regmap_read(priv->regmap, reg_stride * reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return val & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static void rtc7301_write(struct rtc7301_priv *priv, u8 val, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int reg_stride = regmap_get_reg_stride(priv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) regmap_write(priv->regmap, reg_stride * reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static void rtc7301_update_bits(struct rtc7301_priv *priv, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int reg_stride = regmap_get_reg_stride(priv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) regmap_update_bits(priv->regmap, reg_stride * reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int rtc7301_wait_while_busy(struct rtc7301_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int retries = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) while (retries-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) val = rtc7301_read(priv, RTC7301_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (!(val & RTC7301_CONTROL_BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) udelay(300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void rtc7301_stop(struct rtc7301_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) rtc7301_update_bits(priv, RTC7301_CONTROL, RTC7301_CONTROL_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) RTC7301_CONTROL_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void rtc7301_start(struct rtc7301_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) rtc7301_update_bits(priv, RTC7301_CONTROL, RTC7301_CONTROL_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void rtc7301_select_bank(struct rtc7301_priv *priv, u8 bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (bank == priv->bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (bank & BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) val |= RTC7301_CONTROL_BANK_SEL_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (bank & BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) val |= RTC7301_CONTROL_BANK_SEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) rtc7301_update_bits(priv, RTC7301_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) RTC7301_CONTROL_BANK_SEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) RTC7301_CONTROL_BANK_SEL_1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) priv->bank = bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void rtc7301_get_time(struct rtc7301_priv *priv, struct rtc_time *tm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) bool alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) tm->tm_sec = rtc7301_read(priv, RTC7301_1_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) tm->tm_sec += (rtc7301_read(priv, RTC7301_10_SEC) & ~RTC7301_AE) * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) tm->tm_min = rtc7301_read(priv, RTC7301_1_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) tm->tm_min += (rtc7301_read(priv, RTC7301_10_MIN) & ~RTC7301_AE) * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) tm->tm_hour = rtc7301_read(priv, RTC7301_1_HOUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) tm->tm_hour += (rtc7301_read(priv, RTC7301_10_HOUR) & ~RTC7301_AE) * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) tm->tm_mday = rtc7301_read(priv, RTC7301_1_DAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) tm->tm_mday += (rtc7301_read(priv, RTC7301_10_DAY) & ~RTC7301_AE) * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (alarm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) tm->tm_wday = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) tm->tm_mon = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) tm->tm_year = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) tm->tm_yday = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) tm->tm_isdst = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) tm->tm_wday = (rtc7301_read(priv, RTC7301_DAY_OF_WEEK) & ~RTC7301_AE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) tm->tm_mon = rtc7301_read(priv, RTC7301_10_MONTH) * 10 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) rtc7301_read(priv, RTC7301_1_MONTH) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) year = rtc7301_read(priv, RTC7301_1000_YEAR) * 1000 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) rtc7301_read(priv, RTC7301_100_YEAR) * 100 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) rtc7301_read(priv, RTC7301_10_YEAR) * 10 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) rtc7301_read(priv, RTC7301_1_YEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) tm->tm_year = year - 1900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void rtc7301_write_time(struct rtc7301_priv *priv, struct rtc_time *tm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) bool alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) rtc7301_write(priv, tm->tm_sec % 10, RTC7301_1_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) rtc7301_write(priv, tm->tm_sec / 10, RTC7301_10_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) rtc7301_write(priv, tm->tm_min % 10, RTC7301_1_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) rtc7301_write(priv, tm->tm_min / 10, RTC7301_10_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) rtc7301_write(priv, tm->tm_hour % 10, RTC7301_1_HOUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) rtc7301_write(priv, tm->tm_hour / 10, RTC7301_10_HOUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) rtc7301_write(priv, tm->tm_mday % 10, RTC7301_1_DAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) rtc7301_write(priv, tm->tm_mday / 10, RTC7301_10_DAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Don't care for alarm register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) rtc7301_write(priv, alarm ? RTC7301_AE : tm->tm_wday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) RTC7301_DAY_OF_WEEK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) rtc7301_write(priv, (tm->tm_mon + 1) % 10, RTC7301_1_MONTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) rtc7301_write(priv, (tm->tm_mon + 1) / 10, RTC7301_10_MONTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) year = tm->tm_year + 1900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) rtc7301_write(priv, year % 10, RTC7301_1_YEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) rtc7301_write(priv, (year / 10) % 10, RTC7301_10_YEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) rtc7301_write(priv, (year / 100) % 10, RTC7301_100_YEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) rtc7301_write(priv, year / 1000, RTC7301_1000_YEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void rtc7301_alarm_irq(struct rtc7301_priv *priv, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) rtc7301_update_bits(priv, RTC7301_ALARM_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) RTC7301_ALARM_CONTROL_AF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) RTC7301_ALARM_CONTROL_AIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) enabled ? RTC7301_ALARM_CONTROL_AIE : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int rtc7301_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct rtc7301_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) rtc7301_select_bank(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) err = rtc7301_wait_while_busy(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) rtc7301_get_time(priv, tm, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int rtc7301_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct rtc7301_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) rtc7301_stop(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) udelay(300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) rtc7301_select_bank(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) rtc7301_write_time(priv, tm, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) rtc7301_start(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int rtc7301_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct rtc7301_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u8 alrm_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (priv->irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) rtc7301_select_bank(priv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) rtc7301_get_time(priv, &alarm->time, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) alrm_ctrl = rtc7301_read(priv, RTC7301_ALARM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) alarm->enabled = !!(alrm_ctrl & RTC7301_ALARM_CONTROL_AIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) alarm->pending = !!(alrm_ctrl & RTC7301_ALARM_CONTROL_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int rtc7301_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct rtc7301_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (priv->irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) rtc7301_select_bank(priv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) rtc7301_write_time(priv, &alarm->time, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) rtc7301_alarm_irq(priv, alarm->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int rtc7301_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct rtc7301_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (priv->irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) rtc7301_select_bank(priv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) rtc7301_alarm_irq(priv, enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const struct rtc_class_ops rtc7301_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .read_time = rtc7301_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .set_time = rtc7301_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .read_alarm = rtc7301_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .set_alarm = rtc7301_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .alarm_irq_enable = rtc7301_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static irqreturn_t rtc7301_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct rtc_device *rtc = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct rtc7301_priv *priv = dev_get_drvdata(rtc->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u8 alrm_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) rtc7301_select_bank(priv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) alrm_ctrl = rtc7301_read(priv, RTC7301_ALARM_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (alrm_ctrl & RTC7301_ALARM_CONTROL_AF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) rtc7301_alarm_irq(priv, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) rtc_update_irq(rtc, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static void rtc7301_init(struct rtc7301_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) rtc7301_select_bank(priv, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) rtc7301_write(priv, 0, RTC7301_TIMER_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int __init rtc7301_rtc_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct rtc7301_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) regs = devm_platform_ioremap_resource(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) priv->regmap = devm_regmap_init_mmio(&dev->dev, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) &rtc7301_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (IS_ERR(priv->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return PTR_ERR(priv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) priv->irq = platform_get_irq(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) spin_lock_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) priv->bank = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) rtc7301_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) platform_set_drvdata(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) rtc = devm_rtc_device_register(&dev->dev, DRV_NAME, &rtc7301_rtc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (IS_ERR(rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return PTR_ERR(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (priv->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret = devm_request_irq(&dev->dev, priv->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) rtc7301_irq_handler, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dev_name(&dev->dev), rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) priv->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev_err(&dev->dev, "unable to request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) device_set_wakeup_capable(&dev->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int rtc7301_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct rtc7301_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) enable_irq_wake(priv->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int rtc7301_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct rtc7301_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) disable_irq_wake(priv->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static SIMPLE_DEV_PM_OPS(rtc7301_pm_ops, rtc7301_suspend, rtc7301_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static const struct of_device_id rtc7301_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) { .compatible = "epson,rtc7301sf" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) { .compatible = "epson,rtc7301dg" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MODULE_DEVICE_TABLE(of, rtc7301_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static struct platform_driver rtc7301_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .of_match_table = rtc7301_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .pm = &rtc7301_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) module_platform_driver_probe(rtc7301_rtc_driver, rtc7301_rtc_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MODULE_AUTHOR("Akinobu Mita <akinobu.mita@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MODULE_DESCRIPTION("EPSON TOYOCOM RTC-7301SF/DG Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) MODULE_ALIAS("platform:rtc-r7301");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags