Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Real Time Clock interface for XScale PXA27x and PXA3xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2008 Robert Jarzmik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "rtc-sa1100.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define RTC_DEF_DIVIDER		(32768 - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define RTC_DEF_TRIM		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MAXFREQ_PERIODIC	1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * PXA Registers and bits definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define RTSR_PICE	(1 << 15)	/* Periodic interrupt count enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define RTSR_PIALE	(1 << 14)	/* Periodic interrupt Alarm enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define RTSR_PIAL	(1 << 13)	/* Periodic interrupt detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define RTSR_SWALE2	(1 << 11)	/* RTC stopwatch alarm2 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define RTSR_SWAL2	(1 << 10)	/* RTC stopwatch alarm2 detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define RTSR_SWALE1	(1 << 9)	/* RTC stopwatch alarm1 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define RTSR_SWAL1	(1 << 8)	/* RTC stopwatch alarm1 detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define RTSR_RDALE2	(1 << 7)	/* RTC alarm2 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define RTSR_RDAL2	(1 << 6)	/* RTC alarm2 detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define RTSR_RDALE1	(1 << 5)	/* RTC alarm1 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define RTSR_RDAL1	(1 << 4)	/* RTC alarm1 detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define RTSR_HZE	(1 << 3)	/* HZ interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define RTSR_ALE	(1 << 2)	/* RTC alarm interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define RTSR_HZ		(1 << 1)	/* HZ rising-edge detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define RTSR_AL		(1 << 0)	/* RTC alarm detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define RTSR_TRIG_MASK	(RTSR_AL | RTSR_HZ | RTSR_RDAL1 | RTSR_RDAL2\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 			 | RTSR_SWAL1 | RTSR_SWAL2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define RYxR_YEAR_S	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define RYxR_YEAR_MASK	(0xfff << RYxR_YEAR_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define RYxR_MONTH_S	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define RYxR_MONTH_MASK	(0xf << RYxR_MONTH_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define RYxR_DAY_MASK	0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define RDxR_WOM_S     20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define RDxR_WOM_MASK  (0x7 << RDxR_WOM_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define RDxR_DOW_S     17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define RDxR_DOW_MASK  (0x7 << RDxR_DOW_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define RDxR_HOUR_S	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define RDxR_HOUR_MASK	(0x1f << RDxR_HOUR_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define RDxR_MIN_S	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define RDxR_MIN_MASK	(0x3f << RDxR_MIN_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define RDxR_SEC_MASK	0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define RTSR		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define RTTR		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define RDCR		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define RYCR		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define RDAR1		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define RYAR1		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define RTCPICR		0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define PIAR		0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define rtc_readl(pxa_rtc, reg)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	__raw_readl((pxa_rtc)->base + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define rtc_writel(pxa_rtc, reg, value)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	__raw_writel((value), (pxa_rtc)->base + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) struct pxa_rtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct sa1100_rtc sa1100_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct resource	*ress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	void __iomem		*base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct rtc_device	*rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	spinlock_t		lock;		/* Protects this structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static u32 ryxr_calc(struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	return ((tm->tm_year + 1900) << RYxR_YEAR_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		| ((tm->tm_mon + 1) << RYxR_MONTH_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		| tm->tm_mday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static u32 rdxr_calc(struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	return ((((tm->tm_mday + 6) / 7) << RDxR_WOM_S) & RDxR_WOM_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		| (((tm->tm_wday + 1) << RDxR_DOW_S) & RDxR_DOW_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		| (tm->tm_hour << RDxR_HOUR_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		| (tm->tm_min << RDxR_MIN_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		| tm->tm_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void tm_calc(u32 rycr, u32 rdcr, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	tm->tm_year = ((rycr & RYxR_YEAR_MASK) >> RYxR_YEAR_S) - 1900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	tm->tm_mon = (((rycr & RYxR_MONTH_MASK) >> RYxR_MONTH_S)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	tm->tm_mday = (rycr & RYxR_DAY_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	tm->tm_wday = ((rycr & RDxR_DOW_MASK) >> RDxR_DOW_S) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	tm->tm_hour = (rdcr & RDxR_HOUR_MASK) >> RDxR_HOUR_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	tm->tm_min = (rdcr & RDxR_MIN_MASK) >> RDxR_MIN_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	tm->tm_sec = rdcr & RDxR_SEC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void rtsr_clear_bits(struct pxa_rtc *pxa_rtc, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	u32 rtsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	rtsr = rtc_readl(pxa_rtc, RTSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	rtsr &= ~RTSR_TRIG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	rtsr &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	rtc_writel(pxa_rtc, RTSR, rtsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void rtsr_set_bits(struct pxa_rtc *pxa_rtc, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u32 rtsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	rtsr = rtc_readl(pxa_rtc, RTSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	rtsr &= ~RTSR_TRIG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	rtsr |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	rtc_writel(pxa_rtc, RTSR, rtsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static irqreturn_t pxa_rtc_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	u32 rtsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	unsigned long events = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	spin_lock(&pxa_rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	/* clear interrupt sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	rtsr = rtc_readl(pxa_rtc, RTSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	rtc_writel(pxa_rtc, RTSR, rtsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	/* temporary disable rtc interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	rtsr_clear_bits(pxa_rtc, RTSR_RDALE1 | RTSR_PIALE | RTSR_HZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	/* clear alarm interrupt if it has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if (rtsr & RTSR_RDAL1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		rtsr &= ~RTSR_RDALE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/* update irq data & counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (rtsr & RTSR_RDAL1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		events |= RTC_AF | RTC_IRQF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (rtsr & RTSR_HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		events |= RTC_UF | RTC_IRQF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (rtsr & RTSR_PIAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		events |= RTC_PF | RTC_IRQF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	rtc_update_irq(pxa_rtc->rtc, 1, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	/* enable back rtc interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	rtc_writel(pxa_rtc, RTSR, rtsr & ~RTSR_TRIG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	spin_unlock(&pxa_rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int pxa_rtc_open(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	ret = request_irq(pxa_rtc->sa1100_rtc.irq_1hz, pxa_rtc_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			  "rtc 1Hz", dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		dev_err(dev, "can't get irq %i, err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			pxa_rtc->sa1100_rtc.irq_1hz, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		goto err_irq_1Hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	ret = request_irq(pxa_rtc->sa1100_rtc.irq_alarm, pxa_rtc_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			  "rtc Alrm", dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		dev_err(dev, "can't get irq %i, err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			pxa_rtc->sa1100_rtc.irq_alarm, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		goto err_irq_Alrm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) err_irq_Alrm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	free_irq(pxa_rtc->sa1100_rtc.irq_1hz, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) err_irq_1Hz:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void pxa_rtc_release(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	spin_lock_irq(&pxa_rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	spin_unlock_irq(&pxa_rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	free_irq(pxa_rtc->sa1100_rtc.irq_1hz, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	free_irq(pxa_rtc->sa1100_rtc.irq_alarm, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int pxa_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	spin_lock_irq(&pxa_rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		rtsr_set_bits(pxa_rtc, RTSR_RDALE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		rtsr_clear_bits(pxa_rtc, RTSR_RDALE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	spin_unlock_irq(&pxa_rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int pxa_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	u32 rycr, rdcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	rycr = rtc_readl(pxa_rtc, RYCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	rdcr = rtc_readl(pxa_rtc, RDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	tm_calc(rycr, rdcr, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int pxa_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	rtc_writel(pxa_rtc, RYCR, ryxr_calc(tm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	rtc_writel(pxa_rtc, RDCR, rdxr_calc(tm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int pxa_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	u32 rtsr, ryar, rdar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	ryar = rtc_readl(pxa_rtc, RYAR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	rdar = rtc_readl(pxa_rtc, RDAR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	tm_calc(ryar, rdar, &alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	rtsr = rtc_readl(pxa_rtc, RTSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	alrm->enabled = (rtsr & RTSR_RDALE1) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	alrm->pending = (rtsr & RTSR_RDAL1) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int pxa_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	u32 rtsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	spin_lock_irq(&pxa_rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	rtc_writel(pxa_rtc, RYAR1, ryxr_calc(&alrm->time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	rtc_writel(pxa_rtc, RDAR1, rdxr_calc(&alrm->time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	rtsr = rtc_readl(pxa_rtc, RTSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (alrm->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		rtsr |= RTSR_RDALE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		rtsr &= ~RTSR_RDALE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	rtc_writel(pxa_rtc, RTSR, rtsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	spin_unlock_irq(&pxa_rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int pxa_rtc_proc(struct device *dev, struct seq_file *seq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	seq_printf(seq, "trim/divider\t: 0x%08x\n", rtc_readl(pxa_rtc, RTTR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	seq_printf(seq, "update_IRQ\t: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		   (rtc_readl(pxa_rtc, RTSR) & RTSR_HZE) ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	seq_printf(seq, "periodic_IRQ\t: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		   (rtc_readl(pxa_rtc, RTSR) & RTSR_PIALE) ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	seq_printf(seq, "periodic_freq\t: %u\n", rtc_readl(pxa_rtc, PIAR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const struct rtc_class_ops pxa_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	.read_time = pxa_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	.set_time = pxa_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	.read_alarm = pxa_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	.set_alarm = pxa_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	.alarm_irq_enable = pxa_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	.proc = pxa_rtc_proc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int __init pxa_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	struct pxa_rtc *pxa_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	struct sa1100_rtc *sa1100_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	pxa_rtc = devm_kzalloc(dev, sizeof(*pxa_rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	if (!pxa_rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	sa1100_rtc = &pxa_rtc->sa1100_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	spin_lock_init(&pxa_rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	platform_set_drvdata(pdev, pxa_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	pxa_rtc->ress = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	if (!pxa_rtc->ress) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		dev_err(dev, "No I/O memory resource defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	sa1100_rtc->irq_1hz = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	if (sa1100_rtc->irq_1hz < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	sa1100_rtc->irq_alarm = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	if (sa1100_rtc->irq_alarm < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	sa1100_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	if (IS_ERR(sa1100_rtc->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		return PTR_ERR(sa1100_rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	pxa_rtc->base = devm_ioremap(dev, pxa_rtc->ress->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 				resource_size(pxa_rtc->ress));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	if (!pxa_rtc->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		dev_err(dev, "Unable to map pxa RTC I/O memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	pxa_rtc_open(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	sa1100_rtc->rcnr = pxa_rtc->base + 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	sa1100_rtc->rtsr = pxa_rtc->base + 0x8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	sa1100_rtc->rtar = pxa_rtc->base + 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	sa1100_rtc->rttr = pxa_rtc->base + 0xc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	ret = sa1100_rtc_init(pdev, sa1100_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		dev_err(dev, "Unable to init SA1100 RTC sub-device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	pxa_rtc->rtc = devm_rtc_device_register(&pdev->dev, "pxa-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 						&pxa_rtc_ops, THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	if (IS_ERR(pxa_rtc->rtc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		ret = PTR_ERR(pxa_rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		dev_err(dev, "Failed to register RTC device -> %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	device_init_wakeup(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int __exit pxa_rtc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	pxa_rtc_release(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const struct of_device_id pxa_rtc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	{ .compatible = "marvell,pxa-rtc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MODULE_DEVICE_TABLE(of, pxa_rtc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int pxa_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		enable_irq_wake(pxa_rtc->sa1100_rtc.irq_alarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int pxa_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		disable_irq_wake(pxa_rtc->sa1100_rtc.irq_alarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static SIMPLE_DEV_PM_OPS(pxa_rtc_pm_ops, pxa_rtc_suspend, pxa_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static struct platform_driver pxa_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	.remove		= __exit_p(pxa_rtc_remove),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		.name	= "pxa-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		.of_match_table = of_match_ptr(pxa_rtc_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		.pm	= &pxa_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) module_platform_driver_probe(pxa_rtc_driver, pxa_rtc_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MODULE_DESCRIPTION("PXA27x/PXA3xx Realtime Clock Driver (RTC)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MODULE_ALIAS("platform:pxa-rtc");