^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* RTC Register offsets from RTC CTRL REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PM8XXX_ALARM_CTRL_OFFSET 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PM8XXX_RTC_WRITE_OFFSET 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PM8XXX_RTC_READ_OFFSET 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PM8XXX_ALARM_RW_OFFSET 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* RTC_CTRL register bit fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PM8xxx_RTC_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PM8xxx_RTC_ALARM_CLEAR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define NUM_8_BIT_RTC_REGS 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * @ctrl: base address of control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * @write: base address of write register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @read: base address of read register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @alarm_ctrl: base address of alarm control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @alarm_ctrl2: base address of alarm control2 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @alarm_rw: base address of alarm read-write register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @alarm_en: alarm enable mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct pm8xxx_rtc_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int alarm_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned int alarm_ctrl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned int alarm_rw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int alarm_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * struct pm8xxx_rtc - rtc driver internal structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @rtc: rtc device for this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @regmap: regmap used to access RTC registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @allow_set_time: indicates whether writing to the RTC is allowed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @rtc_alarm_irq: rtc alarm irq number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @regs: rtc registers description.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @rtc_dev: device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct pm8xxx_rtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) bool allow_set_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int rtc_alarm_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) const struct pm8xxx_rtc_regs *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct device *rtc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) spinlock_t ctrl_reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Steps to write the RTC registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * 1. Disable alarm if enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * 2. Disable rtc if enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * 3. Write 0x00 to LSB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * 4. Write Byte[1], Byte[2], Byte[3] then Byte[0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * 5. Enable rtc if disabled in step 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * 6. Enable alarm if disabled in step 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int rc, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned long secs, irq_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, rtc_disabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int ctrl_reg, rtc_ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (!rtc_dd->allow_set_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return -EACCES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) secs = rtc_tm_to_time64(tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) value[i] = secs & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) secs >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) goto rtc_rw_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (ctrl_reg & regs->alarm_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) alarm_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ctrl_reg &= ~regs->alarm_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) dev_err(dev, "Write to RTC Alarm control register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) goto rtc_rw_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Disable RTC H/w before writing on RTC register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) rc = regmap_read(rtc_dd->regmap, regs->ctrl, &rtc_ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) goto rtc_rw_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (rtc_ctrl_reg & PM8xxx_RTC_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) rtc_disabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) rtc_ctrl_reg &= ~PM8xxx_RTC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) dev_err(dev, "Write to RTC control register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) goto rtc_rw_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Write 0 to Byte[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) rc = regmap_write(rtc_dd->regmap, regs->write, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dev_err(dev, "Write to RTC write data register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) goto rtc_rw_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Write Byte[1], Byte[2], Byte[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) &value[1], sizeof(value) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) dev_err(dev, "Write to RTC write data register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) goto rtc_rw_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Write Byte[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dev_err(dev, "Write to RTC write data register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) goto rtc_rw_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Enable RTC H/w after writing on RTC register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (rtc_disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) rtc_ctrl_reg |= PM8xxx_RTC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) dev_err(dev, "Write to RTC control register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) goto rtc_rw_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (alarm_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ctrl_reg |= regs->alarm_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dev_err(dev, "Write to RTC Alarm control register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) goto rtc_rw_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) rtc_rw_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u8 value[NUM_8_BIT_RTC_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned long secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dev_err(dev, "RTC read data register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Read the LSB again and check if there has been a carry over.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * If there is, redo the read operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) rc = regmap_read(rtc_dd->regmap, regs->read, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) dev_err(dev, "RTC read data register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (unlikely(reg < value[0])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) rc = regmap_bulk_read(rtc_dd->regmap, regs->read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) value, sizeof(value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dev_err(dev, "RTC read data register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) secs = value[0] | (value[1] << 8) | (value[2] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ((unsigned long)value[3] << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) rtc_time64_to_tm(secs, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dev_dbg(dev, "secs = %lu, h:m:s == %ptRt, y-m-d = %ptRdr\n", secs, tm, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int rc, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u8 value[NUM_8_BIT_RTC_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned long secs, irq_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) secs = rtc_tm_to_time64(&alarm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) value[i] = secs & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) secs >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) sizeof(value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_err(dev, "Write to RTC ALARM register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) goto rtc_rw_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) goto rtc_rw_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (alarm->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ctrl_reg |= regs->alarm_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ctrl_reg &= ~regs->alarm_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dev_err(dev, "Write to RTC alarm control register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) goto rtc_rw_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) dev_dbg(dev, "Alarm Set for h:m:s=%ptRt, y-m-d=%ptRdr\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) &alarm->time, &alarm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) rtc_rw_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u8 value[NUM_8_BIT_RTC_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned long secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) sizeof(value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dev_err(dev, "RTC alarm time read failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) secs = value[0] | (value[1] << 8) | (value[2] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ((unsigned long)value[3] << 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) rtc_time64_to_tm(secs, &alarm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dev_dbg(dev, "Alarm set for - h:m:s=%ptRt, y-m-d=%ptRdr\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) &alarm->time, &alarm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned long irq_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned int ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u8 value[NUM_8_BIT_RTC_REGS] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) goto rtc_rw_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ctrl_reg |= regs->alarm_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ctrl_reg &= ~regs->alarm_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dev_err(dev, "Write to RTC control register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) goto rtc_rw_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Clear Alarm register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (!enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) sizeof(value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev_err(dev, "Clear RTC ALARM register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) goto rtc_rw_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) rtc_rw_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const struct rtc_class_ops pm8xxx_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .read_time = pm8xxx_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .set_time = pm8xxx_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .set_alarm = pm8xxx_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .read_alarm = pm8xxx_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct pm8xxx_rtc *rtc_dd = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned int ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) unsigned long irq_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* Clear the alarm enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) goto rtc_alarm_handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ctrl_reg &= ~regs->alarm_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dev_err(rtc_dd->rtc_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) "Write to alarm control register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) goto rtc_alarm_handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Clear RTC alarm register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dev_err(rtc_dd->rtc_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "RTC Alarm control2 register read failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) goto rtc_alarm_handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dev_err(rtc_dd->rtc_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "Write to RTC Alarm control2 register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) rtc_alarm_handled:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) unsigned int ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* Check if the RTC is on, else turn it on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ctrl_reg |= PM8xxx_RTC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static const struct pm8xxx_rtc_regs pm8921_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .ctrl = 0x11d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .write = 0x11f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .read = 0x123,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .alarm_rw = 0x127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .alarm_ctrl = 0x11d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .alarm_ctrl2 = 0x11e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .alarm_en = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static const struct pm8xxx_rtc_regs pm8058_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .ctrl = 0x1e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .write = 0x1ea,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .read = 0x1ee,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .alarm_rw = 0x1f2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .alarm_ctrl = 0x1e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .alarm_ctrl2 = 0x1e9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .alarm_en = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static const struct pm8xxx_rtc_regs pm8941_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .ctrl = 0x6046,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .write = 0x6040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .read = 0x6048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .alarm_rw = 0x6140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .alarm_ctrl = 0x6146,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .alarm_ctrl2 = 0x6148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .alarm_en = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static const struct of_device_id pm8xxx_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) { .compatible = "qcom,pm8018-rtc", .data = &pm8921_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int pm8xxx_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct pm8xxx_rtc *rtc_dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (rtc_dd == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Initialise spinlock to protect RTC control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) spin_lock_init(&rtc_dd->ctrl_reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (!rtc_dd->regmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev_err(&pdev->dev, "Parent regmap unavailable.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (rtc_dd->rtc_alarm_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) "allow-set-time");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) rtc_dd->regs = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) rtc_dd->rtc_dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) rc = pm8xxx_rtc_enable(rtc_dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) platform_set_drvdata(pdev, rtc_dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* Register the RTC device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) rtc_dd->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (IS_ERR(rtc_dd->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return PTR_ERR(rtc_dd->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) rtc_dd->rtc->ops = &pm8xxx_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) rtc_dd->rtc->range_max = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* Request the alarm IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) pm8xxx_alarm_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) IRQF_TRIGGER_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) "pm8xxx_rtc_alarm", rtc_dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return rtc_register_device(rtc_dd->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int pm8xxx_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) disable_irq_wake(rtc_dd->rtc_alarm_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static int pm8xxx_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) enable_irq_wake(rtc_dd->rtc_alarm_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) pm8xxx_rtc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) pm8xxx_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static struct platform_driver pm8xxx_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .probe = pm8xxx_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .name = "rtc-pm8xxx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .pm = &pm8xxx_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .of_match_table = pm8xxx_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) module_platform_driver(pm8xxx_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) MODULE_ALIAS("platform:rtc-pm8xxx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) MODULE_DESCRIPTION("PMIC8xxx RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags