^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PIC32 RTC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Joshua Henderson <joshua.henderson@microchip.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2016 Microchip Technology Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/mach-pic32/pic32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PIC32_RTCCON 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PIC32_RTCCON_ON BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PIC32_RTCCON_SIDL BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PIC32_RTCCON_RTCCLKSEL (3 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PIC32_RTCCON_RTCCLKON BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PIC32_RTCCON_RTCWREN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PIC32_RTCCON_RTCSYNC BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PIC32_RTCCON_HALFSEC BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PIC32_RTCCON_RTCOE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PIC32_RTCALRM 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PIC32_RTCALRM_ALRMEN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PIC32_RTCALRM_CHIME BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PIC32_RTCALRM_PIV BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PIC32_RTCALRM_ALARMSYNC BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PIC32_RTCALRM_AMASK 0x0F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PIC32_RTCALRM_ARPT 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PIC32_RTCHOUR 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PIC32_RTCMIN 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PIC32_RTCSEC 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PIC32_RTCYEAR 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PIC32_RTCMON 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PIC32_RTCDAY 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PIC32_ALRMTIME 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PIC32_ALRMDATE 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PIC32_ALRMHOUR 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PIC32_ALRMMIN 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PIC32_ALRMSEC 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PIC32_ALRMYEAR 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PIC32_ALRMMON 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PIC32_ALRMDAY 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct pic32_rtc_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) spinlock_t alarm_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int alarm_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) bool alarm_clk_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void pic32_rtc_alarm_clk_enable(struct pic32_rtc_dev *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) spin_lock_irqsave(&pdata->alarm_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (!pdata->alarm_clk_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) clk_enable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pdata->alarm_clk_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (pdata->alarm_clk_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) clk_disable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) pdata->alarm_clk_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) spin_unlock_irqrestore(&pdata->alarm_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static irqreturn_t pic32_rtc_alarmirq(int irq, void *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct pic32_rtc_dev *pdata = (struct pic32_rtc_dev *)id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) clk_enable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) rtc_update_irq(pdata->rtc, 1, RTC_AF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) clk_disable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) pic32_rtc_alarm_clk_enable(pdata, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int pic32_rtc_setaie(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct pic32_rtc_dev *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) void __iomem *base = pdata->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) clk_enable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) writel(PIC32_RTCALRM_ALRMEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) base + (enabled ? PIC32_SET(PIC32_RTCALRM) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PIC32_CLR(PIC32_RTCALRM)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) clk_disable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pic32_rtc_alarm_clk_enable(pdata, enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int pic32_rtc_setfreq(struct device *dev, int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct pic32_rtc_dev *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) void __iomem *base = pdata->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) clk_enable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) writel(PIC32_RTCALRM_AMASK, base + PIC32_CLR(PIC32_RTCALRM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) writel(freq << 8, base + PIC32_SET(PIC32_RTCALRM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) writel(PIC32_RTCALRM_CHIME, base + PIC32_SET(PIC32_RTCALRM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) clk_disable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int pic32_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct pic32_rtc_dev *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void __iomem *base = pdata->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int tries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) clk_enable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) rtc_tm->tm_hour = readb(base + PIC32_RTCHOUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) rtc_tm->tm_min = readb(base + PIC32_RTCMIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) rtc_tm->tm_mon = readb(base + PIC32_RTCMON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) rtc_tm->tm_mday = readb(base + PIC32_RTCDAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) rtc_tm->tm_year = readb(base + PIC32_RTCYEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) rtc_tm->tm_sec = readb(base + PIC32_RTCSEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * The only way to work out whether the system was mid-update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * when we read it is to check the second counter, and if it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * is zero, then we re-try the entire read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) tries += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) } while (rtc_tm->tm_sec == 0 && tries < 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) rtc_tm->tm_sec = bcd2bin(rtc_tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) rtc_tm->tm_min = bcd2bin(rtc_tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) rtc_tm->tm_hour = bcd2bin(rtc_tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) rtc_tm->tm_mday = bcd2bin(rtc_tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) rtc_tm->tm_mon = bcd2bin(rtc_tm->tm_mon) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) rtc_tm->tm_year = bcd2bin(rtc_tm->tm_year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) rtc_tm->tm_year += 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dev_dbg(dev, "read time %ptR\n", rtc_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) clk_disable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int pic32_rtc_settime(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct pic32_rtc_dev *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) void __iomem *base = pdata->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dev_dbg(dev, "set time %ptR\n", tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) clk_enable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) writeb(bin2bcd(tm->tm_sec), base + PIC32_RTCSEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) writeb(bin2bcd(tm->tm_min), base + PIC32_RTCMIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) writeb(bin2bcd(tm->tm_hour), base + PIC32_RTCHOUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) writeb(bin2bcd(tm->tm_mday), base + PIC32_RTCDAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) writeb(bin2bcd(tm->tm_mon + 1), base + PIC32_RTCMON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) writeb(bin2bcd(tm->tm_year - 100), base + PIC32_RTCYEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) clk_disable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int pic32_rtc_getalarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct pic32_rtc_dev *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct rtc_time *alm_tm = &alrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) void __iomem *base = pdata->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int alm_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) clk_enable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) alm_tm->tm_sec = readb(base + PIC32_ALRMSEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) alm_tm->tm_min = readb(base + PIC32_ALRMMIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) alm_tm->tm_hour = readb(base + PIC32_ALRMHOUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) alm_tm->tm_mon = readb(base + PIC32_ALRMMON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) alm_tm->tm_mday = readb(base + PIC32_ALRMDAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) alm_tm->tm_year = readb(base + PIC32_ALRMYEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) alm_en = readb(base + PIC32_RTCALRM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) alrm->enabled = (alm_en & PIC32_RTCALRM_ALRMEN) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dev_dbg(dev, "getalarm: %d, %ptR\n", alm_en, alm_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) alm_tm->tm_sec = bcd2bin(alm_tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) alm_tm->tm_min = bcd2bin(alm_tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) alm_tm->tm_hour = bcd2bin(alm_tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) alm_tm->tm_mday = bcd2bin(alm_tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) alm_tm->tm_mon = bcd2bin(alm_tm->tm_mon) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) alm_tm->tm_year = bcd2bin(alm_tm->tm_year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) clk_disable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int pic32_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct pic32_rtc_dev *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct rtc_time *tm = &alrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) void __iomem *base = pdata->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) clk_enable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_dbg(dev, "setalarm: %d, %ptR\n", alrm->enabled, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) writel(0x00, base + PIC32_ALRMTIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) writel(0x00, base + PIC32_ALRMDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) pic32_rtc_setaie(dev, alrm->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) clk_disable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int pic32_rtc_proc(struct device *dev, struct seq_file *seq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct pic32_rtc_dev *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) void __iomem *base = pdata->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned int repeat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) clk_enable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) repeat = readw(base + PIC32_RTCALRM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) repeat &= PIC32_RTCALRM_ARPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) seq_printf(seq, "periodic_IRQ\t: %s\n", repeat ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) clk_disable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const struct rtc_class_ops pic32_rtcops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .read_time = pic32_rtc_gettime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .set_time = pic32_rtc_settime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .read_alarm = pic32_rtc_getalarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .set_alarm = pic32_rtc_setalarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .proc = pic32_rtc_proc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .alarm_irq_enable = pic32_rtc_setaie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static void pic32_rtc_enable(struct pic32_rtc_dev *pdata, int en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) void __iomem *base = pdata->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (!base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) clk_enable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (!en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) writel(PIC32_RTCCON_ON, base + PIC32_CLR(PIC32_RTCCON));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pic32_syskey_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) writel(PIC32_RTCCON_RTCWREN, base + PIC32_SET(PIC32_RTCCON));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) writel(3 << 9, base + PIC32_CLR(PIC32_RTCCON));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (!(readl(base + PIC32_RTCCON) & PIC32_RTCCON_ON))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) writel(PIC32_RTCCON_ON, base + PIC32_SET(PIC32_RTCCON));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) clk_disable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int pic32_rtc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct pic32_rtc_dev *pdata = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) pic32_rtc_setaie(&pdev->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) clk_unprepare(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) pdata->clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int pic32_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct pic32_rtc_dev *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) platform_set_drvdata(pdev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pdata->alarm_irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (pdata->alarm_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return pdata->alarm_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pdata->reg_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (IS_ERR(pdata->reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return PTR_ERR(pdata->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) pdata->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (IS_ERR(pdata->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dev_err(&pdev->dev, "failed to find rtc clock source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret = PTR_ERR(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pdata->clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) spin_lock_init(&pdata->alarm_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) clk_prepare_enable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) pic32_rtc_enable(pdata, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (IS_ERR(pdata->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return PTR_ERR(pdata->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) pdata->rtc->ops = &pic32_rtcops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) pdata->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) pdata->rtc->range_max = RTC_TIMESTAMP_END_2099;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = rtc_register_device(pdata->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) goto err_nortc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) pdata->rtc->max_user_freq = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) pic32_rtc_setfreq(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ret = devm_request_irq(&pdev->dev, pdata->alarm_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) pic32_rtc_alarmirq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev_name(&pdev->dev), pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) "IRQ %d error %d\n", pdata->alarm_irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) goto err_nortc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) clk_disable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) err_nortc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) pic32_rtc_enable(pdata, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) clk_disable_unprepare(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const struct of_device_id pic32_rtc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) { .compatible = "microchip,pic32mzda-rtc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) MODULE_DEVICE_TABLE(of, pic32_rtc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static struct platform_driver pic32_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .probe = pic32_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .remove = pic32_rtc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .name = "pic32-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .of_match_table = of_match_ptr(pic32_rtc_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) module_platform_driver(pic32_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MODULE_DESCRIPTION("Microchip PIC32 RTC Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MODULE_AUTHOR("Joshua Henderson <joshua.henderson@microchip.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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