^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/rtc/rtc-pcf85363.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Driver for NXP PCF85363 real-time clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2017 Eric Nelson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Date/Time registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DT_100THS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DT_SECS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DT_MINUTES 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DT_HOURS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DT_DAYS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DT_WEEKDAYS 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DT_MONTHS 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DT_YEARS 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Alarm registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DT_SECOND_ALM1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DT_MINUTE_ALM1 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DT_HOUR_ALM1 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DT_DAY_ALM1 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DT_MONTH_ALM1 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DT_MINUTE_ALM2 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DT_HOUR_ALM2 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DT_WEEKDAY_ALM2 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DT_ALARM_EN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Time stamp registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DT_TIMESTAMP1 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DT_TIMESTAMP2 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DT_TIMESTAMP3 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DT_TS_MODE 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * control registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CTRL_OFFSET 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CTRL_OSCILLATOR 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CTRL_BATTERY 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CTRL_PIN_IO 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CTRL_FUNCTION 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CTRL_INTA_EN 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CTRL_INTB_EN 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CTRL_FLAGS 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CTRL_RAMBYTE 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CTRL_WDOG 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CTRL_STOP_EN 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CTRL_RESETS 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CTRL_RAM 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ALRM_SEC_A1E BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ALRM_MIN_A1E BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ALRM_HR_A1E BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ALRM_DAY_A1E BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ALRM_MON_A1E BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ALRM_MIN_A2E BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ALRM_HR_A2E BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ALRM_DAY_A2E BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define INT_WDIE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define INT_BSIE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define INT_TSRIE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define INT_A2IE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define INT_A1IE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define INT_OIE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define INT_PIE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define INT_ILP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define FLAGS_TSR1F BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define FLAGS_TSR2F BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define FLAGS_TSR3F BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define FLAGS_BSF BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define FLAGS_WDF BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define FLAGS_A1F BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define FLAGS_A2F BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define FLAGS_PIF BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PIN_IO_INTAPM GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PIN_IO_INTA_CLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PIN_IO_INTA_BAT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PIN_IO_INTA_OUT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PIN_IO_INTA_HIZ 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define STOP_EN_STOP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RESET_CPR 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define NVRAM_SIZE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct pcf85363 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct pcf85x63_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct regmap_config regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int num_nvram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int pcf85363_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned char buf[DT_YEARS + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int ret, len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* read the RTC date and time registers all at once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ret = regmap_bulk_read(pcf85363->regmap, DT_100THS, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dev_err(dev, "%s: error %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) tm->tm_year = bcd2bin(buf[DT_YEARS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* adjust for 1900 base of rtc_time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) tm->tm_year += 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) tm->tm_wday = buf[DT_WEEKDAYS] & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) buf[DT_SECS] &= 0x7F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) tm->tm_sec = bcd2bin(buf[DT_SECS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) buf[DT_MINUTES] &= 0x7F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) tm->tm_min = bcd2bin(buf[DT_MINUTES]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) tm->tm_hour = bcd2bin(buf[DT_HOURS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) tm->tm_mday = bcd2bin(buf[DT_DAYS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) tm->tm_mon = bcd2bin(buf[DT_MONTHS]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int pcf85363_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned char tmp[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned char *buf = &tmp[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) tmp[0] = STOP_EN_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) tmp[1] = RESET_CPR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) buf[DT_100THS] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) buf[DT_SECS] = bin2bcd(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) buf[DT_MINUTES] = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) buf[DT_HOURS] = bin2bcd(tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) buf[DT_DAYS] = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) buf[DT_WEEKDAYS] = tm->tm_wday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) buf[DT_MONTHS] = bin2bcd(tm->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) buf[DT_YEARS] = bin2bcd(tm->tm_year % 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ret = regmap_bulk_write(pcf85363->regmap, CTRL_STOP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) tmp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = regmap_bulk_write(pcf85363->regmap, DT_100THS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) buf, sizeof(tmp) - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return regmap_write(pcf85363->regmap, CTRL_STOP_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int pcf85363_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned char buf[DT_MONTH_ALM1 - DT_SECOND_ALM1 + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ret = regmap_bulk_read(pcf85363->regmap, DT_SECOND_ALM1, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) alrm->time.tm_sec = bcd2bin(buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) alrm->time.tm_min = bcd2bin(buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) alrm->time.tm_hour = bcd2bin(buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) alrm->time.tm_mday = bcd2bin(buf[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) alrm->time.tm_mon = bcd2bin(buf[4]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ret = regmap_read(pcf85363->regmap, CTRL_INTA_EN, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) alrm->enabled = !!(val & INT_A1IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int _pcf85363_rtc_alarm_irq_enable(struct pcf85363 *pcf85363, unsigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int alarm_flags = ALRM_SEC_A1E | ALRM_MIN_A1E | ALRM_HR_A1E |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ALRM_DAY_A1E | ALRM_MON_A1E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ret = regmap_update_bits(pcf85363->regmap, DT_ALARM_EN, alarm_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) enabled ? alarm_flags : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = regmap_update_bits(pcf85363->regmap, CTRL_INTA_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) INT_A1IE, enabled ? INT_A1IE : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret || enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* clear current flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return regmap_update_bits(pcf85363->regmap, CTRL_FLAGS, FLAGS_A1F, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int pcf85363_rtc_alarm_irq_enable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return _pcf85363_rtc_alarm_irq_enable(pcf85363, enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int pcf85363_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct pcf85363 *pcf85363 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned char buf[DT_MONTH_ALM1 - DT_SECOND_ALM1 + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) buf[0] = bin2bcd(alrm->time.tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) buf[1] = bin2bcd(alrm->time.tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) buf[2] = bin2bcd(alrm->time.tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) buf[3] = bin2bcd(alrm->time.tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) buf[4] = bin2bcd(alrm->time.tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * Disable the alarm interrupt before changing the value to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * spurious interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ret = _pcf85363_rtc_alarm_irq_enable(pcf85363, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = regmap_bulk_write(pcf85363->regmap, DT_SECOND_ALM1, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return _pcf85363_rtc_alarm_irq_enable(pcf85363, alrm->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static irqreturn_t pcf85363_rtc_handle_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct pcf85363 *pcf85363 = i2c_get_clientdata(dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) err = regmap_read(pcf85363->regmap, CTRL_FLAGS, &flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (flags & FLAGS_A1F) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) rtc_update_irq(pcf85363->rtc, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) regmap_update_bits(pcf85363->regmap, CTRL_FLAGS, FLAGS_A1F, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct rtc_class_ops rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .read_time = pcf85363_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .set_time = pcf85363_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const struct rtc_class_ops rtc_ops_alarm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .read_time = pcf85363_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .set_time = pcf85363_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .read_alarm = pcf85363_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .set_alarm = pcf85363_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .alarm_irq_enable = pcf85363_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int pcf85363_nvram_read(void *priv, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct pcf85363 *pcf85363 = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return regmap_bulk_read(pcf85363->regmap, CTRL_RAM + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) val, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int pcf85363_nvram_write(void *priv, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct pcf85363 *pcf85363 = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return regmap_bulk_write(pcf85363->regmap, CTRL_RAM + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) val, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int pcf85x63_nvram_read(void *priv, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct pcf85363 *pcf85363 = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned int tmp_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ret = regmap_read(pcf85363->regmap, CTRL_RAMBYTE, &tmp_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) (*(unsigned char *) val) = (unsigned char) tmp_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int pcf85x63_nvram_write(void *priv, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct pcf85363 *pcf85363 = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned char tmp_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) tmp_val = *((unsigned char *)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return regmap_write(pcf85363->regmap, CTRL_RAMBYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) (unsigned int)tmp_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const struct pcf85x63_config pcf_85263_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .regmap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .max_register = 0x2f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .num_nvram = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const struct pcf85x63_config pcf_85363_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .regmap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .max_register = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .num_nvram = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int pcf85363_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct pcf85363 *pcf85363;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) const struct pcf85x63_config *config = &pcf_85363_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) const void *data = of_device_get_match_data(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static struct nvmem_config nvmem_cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .name = "pcf85x63-",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .word_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .reg_read = pcf85x63_nvram_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .reg_write = pcf85x63_nvram_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .name = "pcf85363-",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .word_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .size = NVRAM_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .reg_read = pcf85363_nvram_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .reg_write = pcf85363_nvram_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) config = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) pcf85363 = devm_kzalloc(&client->dev, sizeof(struct pcf85363),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (!pcf85363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) pcf85363->regmap = devm_regmap_init_i2c(client, &config->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (IS_ERR(pcf85363->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_err(&client->dev, "regmap allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return PTR_ERR(pcf85363->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) i2c_set_clientdata(client, pcf85363);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pcf85363->rtc = devm_rtc_allocate_device(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (IS_ERR(pcf85363->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return PTR_ERR(pcf85363->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) pcf85363->rtc->ops = &rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) pcf85363->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) pcf85363->rtc->range_max = RTC_TIMESTAMP_END_2099;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (client->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) regmap_write(pcf85363->regmap, CTRL_FLAGS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) regmap_update_bits(pcf85363->regmap, CTRL_PIN_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) PIN_IO_INTA_OUT, PIN_IO_INTAPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ret = devm_request_threaded_irq(&client->dev, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) NULL, pcf85363_rtc_handle_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) IRQF_TRIGGER_LOW | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) "pcf85363", client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dev_warn(&client->dev, "unable to request IRQ, alarms disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) pcf85363->rtc->ops = &rtc_ops_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ret = rtc_register_device(pcf85363->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) for (i = 0; i < config->num_nvram; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) nvmem_cfg[i].priv = pcf85363;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) rtc_nvmem_register(pcf85363->rtc, &nvmem_cfg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const struct of_device_id dev_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) { .compatible = "nxp,pcf85263", .data = &pcf_85263_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) { .compatible = "nxp,pcf85363", .data = &pcf_85363_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) MODULE_DEVICE_TABLE(of, dev_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static struct i2c_driver pcf85363_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .name = "pcf85363",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .of_match_table = of_match_ptr(dev_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .probe = pcf85363_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) module_i2c_driver(pcf85363_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MODULE_AUTHOR("Eric Nelson");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MODULE_DESCRIPTION("pcf85263/pcf85363 I2C RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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