^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * An I2C driver for the PCF85063 RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2014 Rose Technology
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Søren Andersen <san@rosetechnology.dk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Maintainers: http://www.nslu2-linux.org/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2019 Micro Crystal AG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Author: Alexandre Belloni <alexandre.belloni@bootlin.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_wakeirq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Information for this driver was pulled from the following datasheets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * https://www.nxp.com/documents/data_sheet/PCF85063A.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * https://www.nxp.com/documents/data_sheet/PCF85063TP.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * PCF85063A -- Rev. 6 — 18 November 2015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * PCF85063TP -- Rev. 4 — 6 May 2015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * https://www.microcrystal.com/fileadmin/Media/Products/RTC/App.Manual/RV-8263-C7_App-Manual.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * RV8263 -- Rev. 1.0 — January 2019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCF85063_REG_CTRL1 0x00 /* status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCF85063_REG_CTRL1_CAP_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCF85063_REG_CTRL1_STOP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCF85063_REG_CTRL2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCF85063_CTRL2_AF BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCF85063_CTRL2_AIE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCF85063_REG_OFFSET 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCF85063_OFFSET_SIGN_BIT 6 /* 2's complement sign bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCF85063_OFFSET_MODE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCF85063_OFFSET_STEP0 4340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PCF85063_OFFSET_STEP1 4069
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCF85063_REG_CLKO_F_MASK 0x07 /* frequency mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCF85063_REG_CLKO_F_32768HZ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCF85063_REG_CLKO_F_OFF 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCF85063_REG_RAM 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PCF85063_REG_SC 0x04 /* datetime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCF85063_REG_SC_OS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PCF85063_REG_ALM_S 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCF85063_AEN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct pcf85063_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct regmap_config regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned has_alarms:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned force_cap_7000:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct pcf85063 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #ifdef CONFIG_COMMON_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct clk_hw clkout_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int pcf85063_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 regs[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * while reading, the time/date registers are blocked and not updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * anymore until the access is finished. To not lose a second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * event, the access must be finished within one second. So, read all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * time/date registers in one turn.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) rc = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_SC, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) sizeof(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* if the clock has lost its power it makes no sense to use its time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (regs[0] & PCF85063_REG_SC_OS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dev_warn(&pcf85063->rtc->dev, "Power loss detected, invalid time\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) tm->tm_sec = bcd2bin(regs[0] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) tm->tm_min = bcd2bin(regs[1] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) tm->tm_hour = bcd2bin(regs[2] & 0x3F); /* rtc hr 0-23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) tm->tm_mday = bcd2bin(regs[3] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) tm->tm_wday = regs[4] & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) tm->tm_mon = bcd2bin(regs[5] & 0x1F) - 1; /* rtc mn 1-12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) tm->tm_year = bcd2bin(regs[6]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) tm->tm_year += 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int pcf85063_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 regs[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * to accurately set the time, reset the divider chain and keep it in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * reset state until all time/date registers are written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) rc = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PCF85063_REG_CTRL1_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PCF85063_REG_CTRL1_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* hours, minutes and seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) regs[0] = bin2bcd(tm->tm_sec) & 0x7F; /* clear OS flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) regs[1] = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) regs[2] = bin2bcd(tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Day of month, 1 - 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) regs[3] = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Day, 0 - 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) regs[4] = tm->tm_wday & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* month, 1 - 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) regs[5] = bin2bcd(tm->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* year and century */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) regs[6] = bin2bcd(tm->tm_year - 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* write all registers at once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) rc = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_SC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) regs, sizeof(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * Write the control register as a separate action since the size of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * the register space is different between the PCF85063TP and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * PCF85063A devices. The rollover point can not be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PCF85063_REG_CTRL1_STOP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int pcf85063_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u8 buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ret = regmap_bulk_read(pcf85063->regmap, PCF85063_REG_ALM_S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) alrm->time.tm_sec = bcd2bin(buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) alrm->time.tm_min = bcd2bin(buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) alrm->time.tm_hour = bcd2bin(buf[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) alrm->time.tm_mday = bcd2bin(buf[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) alrm->enabled = !!(val & PCF85063_CTRL2_AIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int pcf85063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u8 buf[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) buf[0] = bin2bcd(alrm->time.tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) buf[1] = bin2bcd(alrm->time.tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) buf[2] = bin2bcd(alrm->time.tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) buf[3] = bin2bcd(alrm->time.tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) buf[4] = PCF85063_AEN; /* Do not match on week day */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ret = regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ret = regmap_bulk_write(pcf85063->regmap, PCF85063_REG_ALM_S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) alrm->enabled ? PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF : PCF85063_CTRL2_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int pcf85063_rtc_alarm_irq_enable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PCF85063_CTRL2_AIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) enabled ? PCF85063_CTRL2_AIE : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static irqreturn_t pcf85063_rtc_handle_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct pcf85063 *pcf85063 = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (val & PCF85063_CTRL2_AF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) rtc_update_irq(pcf85063->rtc, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PCF85063_CTRL2_AIE | PCF85063_CTRL2_AF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int pcf85063_read_offset(struct device *dev, long *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) val = sign_extend32(reg & ~PCF85063_OFFSET_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PCF85063_OFFSET_SIGN_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (reg & PCF85063_OFFSET_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) *offset = val * PCF85063_OFFSET_STEP1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) *offset = val * PCF85063_OFFSET_STEP0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int pcf85063_set_offset(struct device *dev, long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) s8 mode0, mode1, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned int error0, error1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (offset > PCF85063_OFFSET_STEP0 * 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (offset < PCF85063_OFFSET_STEP0 * -64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) mode0 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mode1 = DIV_ROUND_CLOSEST(offset, PCF85063_OFFSET_STEP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) error0 = abs(offset - (mode0 * PCF85063_OFFSET_STEP0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) error1 = abs(offset - (mode1 * PCF85063_OFFSET_STEP1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (mode1 > 63 || mode1 < -64 || error0 < error1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) reg = mode0 & ~PCF85063_OFFSET_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) reg = mode1 | PCF85063_OFFSET_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return regmap_write(pcf85063->regmap, PCF85063_REG_OFFSET, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int pcf85063_ioctl(struct device *dev, unsigned int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct pcf85063 *pcf85063 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int status, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case RTC_VL_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ret = regmap_read(pcf85063->regmap, PCF85063_REG_SC, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) status = status & PCF85063_REG_SC_OS ? RTC_VL_DATA_INVALID : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return put_user(status, (unsigned int __user *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static const struct rtc_class_ops pcf85063_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .read_time = pcf85063_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .set_time = pcf85063_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .read_offset = pcf85063_read_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .set_offset = pcf85063_set_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .ioctl = pcf85063_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static const struct rtc_class_ops pcf85063_rtc_ops_alarm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .read_time = pcf85063_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .set_time = pcf85063_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .read_offset = pcf85063_read_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .set_offset = pcf85063_set_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .read_alarm = pcf85063_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .set_alarm = pcf85063_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .alarm_irq_enable = pcf85063_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .ioctl = pcf85063_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int pcf85063_nvmem_read(void *priv, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) void *val, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return regmap_read(priv, PCF85063_REG_RAM, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int pcf85063_nvmem_write(void *priv, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) void *val, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return regmap_write(priv, PCF85063_REG_RAM, *(u8 *)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int pcf85063_load_capacitance(struct pcf85063 *pcf85063,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) const struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned int force_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 load = 7000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u8 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (force_cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) load = force_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) of_property_read_u32(np, "quartz-load-femtofarads", &load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) switch (load) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dev_warn(&pcf85063->rtc->dev, "Unknown quartz-load-femtofarads value: %d. Assuming 7000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case 7000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) case 12500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) reg = PCF85063_REG_CTRL1_CAP_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) PCF85063_REG_CTRL1_CAP_SEL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #ifdef CONFIG_COMMON_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * Handling of the clkout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define clkout_hw_to_pcf85063(_hw) container_of(_hw, struct pcf85063, clkout_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int clkout_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 32768,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 16384,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 8192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static unsigned long pcf85063_clkout_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned int buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) buf &= PCF85063_REG_CLKO_F_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return clkout_rates[buf];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static long pcf85063_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (clkout_rates[i] <= rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return clkout_rates[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static int pcf85063_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) for (i = 0; i < ARRAY_SIZE(clkout_rates); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (clkout_rates[i] == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return regmap_update_bits(pcf85063->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PCF85063_REG_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PCF85063_REG_CLKO_F_MASK, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int pcf85063_clkout_control(struct clk_hw *hw, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned int buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ret = regmap_read(pcf85063->regmap, PCF85063_REG_OFFSET, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) buf &= PCF85063_REG_CLKO_F_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (buf == PCF85063_REG_CLKO_F_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) buf = PCF85063_REG_CLKO_F_32768HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (buf != PCF85063_REG_CLKO_F_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) buf = PCF85063_REG_CLKO_F_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return regmap_update_bits(pcf85063->regmap, PCF85063_REG_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) PCF85063_REG_CLKO_F_MASK, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static int pcf85063_clkout_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return pcf85063_clkout_control(hw, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static void pcf85063_clkout_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pcf85063_clkout_control(hw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int pcf85063_clkout_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct pcf85063 *pcf85063 = clkout_hw_to_pcf85063(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) unsigned int buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int ret = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL2, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return (buf & PCF85063_REG_CLKO_F_MASK) != PCF85063_REG_CLKO_F_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static const struct clk_ops pcf85063_clkout_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .prepare = pcf85063_clkout_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .unprepare = pcf85063_clkout_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .is_prepared = pcf85063_clkout_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .recalc_rate = pcf85063_clkout_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .round_rate = pcf85063_clkout_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .set_rate = pcf85063_clkout_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static struct clk *pcf85063_clkout_register_clk(struct pcf85063 *pcf85063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct device_node *node = pcf85063->rtc->dev.parent->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) init.name = "pcf85063-clkout";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) init.ops = &pcf85063_clkout_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) init.parent_names = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) init.num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) pcf85063->clkout_hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* optional override of the clockname */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) of_property_read_string(node, "clock-output-names", &init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* register the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) clk = devm_clk_register(&pcf85063->rtc->dev, &pcf85063->clkout_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (!IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) of_clk_add_provider(node, of_clk_src_simple_get, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static const struct pcf85063_config pcf85063a_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .regmap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .max_register = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .has_alarms = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static const struct pcf85063_config pcf85063tp_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .regmap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .max_register = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static const struct pcf85063_config rv8263_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .regmap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .max_register = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .has_alarms = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .force_cap_7000 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static int pcf85063_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct pcf85063 *pcf85063;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) const struct pcf85063_config *config = &pcf85063tp_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) const void *data = of_device_get_match_data(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct nvmem_config nvmem_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .name = "pcf85063_nvram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .reg_read = pcf85063_nvmem_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .reg_write = pcf85063_nvmem_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .type = NVMEM_TYPE_BATTERY_BACKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) dev_dbg(&client->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) pcf85063 = devm_kzalloc(&client->dev, sizeof(struct pcf85063),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (!pcf85063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) config = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) pcf85063->regmap = devm_regmap_init_i2c(client, &config->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (IS_ERR(pcf85063->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return PTR_ERR(pcf85063->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) i2c_set_clientdata(client, pcf85063);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) err = regmap_read(pcf85063->regmap, PCF85063_REG_CTRL1, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dev_err(&client->dev, "RTC chip is not present\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) pcf85063->rtc = devm_rtc_allocate_device(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (IS_ERR(pcf85063->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return PTR_ERR(pcf85063->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) err = pcf85063_load_capacitance(pcf85063, client->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) config->force_cap_7000 ? 7000 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) dev_warn(&client->dev, "failed to set xtal load capacitance: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) pcf85063->rtc->ops = &pcf85063_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) pcf85063->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) pcf85063->rtc->range_max = RTC_TIMESTAMP_END_2099;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) pcf85063->rtc->uie_unsupported = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (config->has_alarms && client->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) err = devm_request_threaded_irq(&client->dev, client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) NULL, pcf85063_rtc_handle_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) IRQF_TRIGGER_LOW | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) "pcf85063", pcf85063);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dev_warn(&pcf85063->rtc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) "unable to request IRQ, alarms disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) pcf85063->rtc->ops = &pcf85063_rtc_ops_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) device_init_wakeup(&client->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) err = dev_pm_set_wake_irq(&client->dev, client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) dev_err(&pcf85063->rtc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) "failed to enable irq wake\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) nvmem_cfg.priv = pcf85063->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) rtc_nvmem_register(pcf85063->rtc, &nvmem_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #ifdef CONFIG_COMMON_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* register clk in common clk framework */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) pcf85063_clkout_register_clk(pcf85063);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return rtc_register_device(pcf85063->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static const struct of_device_id pcf85063_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) { .compatible = "nxp,pcf85063", .data = &pcf85063tp_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) { .compatible = "nxp,pcf85063tp", .data = &pcf85063tp_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) { .compatible = "nxp,pcf85063a", .data = &pcf85063a_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) { .compatible = "microcrystal,rv8263", .data = &rv8263_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) MODULE_DEVICE_TABLE(of, pcf85063_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static struct i2c_driver pcf85063_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .name = "rtc-pcf85063",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .of_match_table = of_match_ptr(pcf85063_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .probe_new = pcf85063_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) module_i2c_driver(pcf85063_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) MODULE_AUTHOR("Søren Andersen <san@rosetechnology.dk>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) MODULE_DESCRIPTION("PCF85063 RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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