Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * An SPI driver for the Philips PCF2123 RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright 2009 Cyber Switching, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Chris Verges <chrisv@cyberswitching.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Maintainers: http://www.cyberswitching.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * based on the RS5C348 driver in this same directory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Thanks to Christian Pellegrin <chripell@fsfe.org> for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * the sysfs contributions to this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Please note that the CS is active high, so platform data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * should look something like:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * static struct spi_board_info ek_spi_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *	...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *		.modalias		= "rtc-pcf2123",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *		.chip_select		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *		.controller_data	= (void *)AT91_PIN_PA10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *		.max_speed_hz		= 1000 * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *		.mode			= SPI_CS_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *		.bus_num		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *	...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* REGISTERS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PCF2123_REG_CTRL1	(0x00)	/* Control Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PCF2123_REG_CTRL2	(0x01)	/* Control Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define PCF2123_REG_SC		(0x02)	/* datetime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define PCF2123_REG_MN		(0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PCF2123_REG_HR		(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define PCF2123_REG_DM		(0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define PCF2123_REG_DW		(0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define PCF2123_REG_MO		(0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define PCF2123_REG_YR		(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define PCF2123_REG_ALRM_MN	(0x09)	/* Alarm Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PCF2123_REG_ALRM_HR	(0x0a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define PCF2123_REG_ALRM_DM	(0x0b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define PCF2123_REG_ALRM_DW	(0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define PCF2123_REG_OFFSET	(0x0d)	/* Clock Rate Offset Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define PCF2123_REG_TMR_CLKOUT	(0x0e)	/* Timer Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define PCF2123_REG_CTDWN_TMR	(0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* PCF2123_REG_CTRL1 BITS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CTRL1_CLEAR		(0)	/* Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CTRL1_CORR_INT		BIT(1)	/* Correction irq enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CTRL1_12_HOUR		BIT(2)	/* 12 hour time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define CTRL1_SW_RESET	(BIT(3) | BIT(4) | BIT(6))	/* Software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define CTRL1_STOP		BIT(5)	/* Stop the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CTRL1_EXT_TEST		BIT(7)	/* External clock test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /* PCF2123_REG_CTRL2 BITS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define CTRL2_TIE		BIT(0)	/* Countdown timer irq enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CTRL2_AIE		BIT(1)	/* Alarm irq enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define CTRL2_TF		BIT(2)	/* Countdown timer flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define CTRL2_AF		BIT(3)	/* Alarm flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define CTRL2_TI_TP		BIT(4)	/* Irq pin generates pulse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define CTRL2_MSF		BIT(5)	/* Minute or second irq flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define CTRL2_SI		BIT(6)	/* Second irq enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define CTRL2_MI		BIT(7)	/* Minute irq enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* PCF2123_REG_SC BITS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define OSC_HAS_STOPPED		BIT(7)	/* Clock has been stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /* PCF2123_REG_ALRM_XX BITS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define ALRM_DISABLE		BIT(7)	/* MN, HR, DM, or DW alarm matching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /* PCF2123_REG_TMR_CLKOUT BITS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CD_TMR_4096KHZ		(0)	/* 4096 KHz countdown timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CD_TMR_64HZ		(1)	/* 64 Hz countdown timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CD_TMR_1HZ		(2)	/* 1 Hz countdown timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CD_TMR_60th_HZ		(3)	/* 60th Hz countdown timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define CD_TMR_TE		BIT(3)	/* Countdown timer enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) /* PCF2123_REG_OFFSET BITS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define OFFSET_SIGN_BIT		6	/* 2's complement sign bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define OFFSET_COARSE		BIT(7)	/* Coarse mode offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define OFFSET_STEP		(2170)	/* Offset step in parts per billion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define OFFSET_MASK		GENMASK(6, 0)	/* Offset value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* READ/WRITE ADDRESS BITS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PCF2123_WRITE		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PCF2123_READ		(BIT(4) | BIT(7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static struct spi_driver pcf2123_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct pcf2123_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const struct regmap_config pcf2123_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.read_flag_mask = PCF2123_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.write_flag_mask = PCF2123_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.max_register = PCF2123_REG_CTDWN_TMR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int pcf2123_read_offset(struct device *dev, long *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	int ret, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	ret = regmap_read(pcf2123->map, PCF2123_REG_OFFSET, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	val = sign_extend32((reg & OFFSET_MASK), OFFSET_SIGN_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	if (reg & OFFSET_COARSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		val *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	*offset = ((long)val) * OFFSET_STEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  * The offset register is a 7 bit signed value with a coarse bit in bit 7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  * The main difference between the two is normal offset adjusts the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  * second of n minutes every other hour, with 61, 62 and 63 being shoved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * into the 60th minute.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  * The coarse adjustment does the same, but every hour.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  * the two overlap, with every even normal offset value corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  * to a coarse offset. Based on this algorithm, it seems that despite the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  * name, coarse offset is a better fit for overlapping values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int pcf2123_set_offset(struct device *dev, long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	s8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (offset > OFFSET_STEP * 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		reg = 127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	else if (offset < OFFSET_STEP * -128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		reg = -128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		reg = DIV_ROUND_CLOSEST(offset, OFFSET_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	/* choose fine offset only for odd values in the normal range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (reg & 1 && reg <= 63 && reg >= -64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		/* Normal offset. Clear the coarse bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		reg &= ~OFFSET_COARSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		/* Coarse offset. Divide by 2 and set the coarse bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		reg >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		reg |= OFFSET_COARSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	return regmap_write(pcf2123->map, PCF2123_REG_OFFSET, (unsigned int)reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int pcf2123_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	u8 rxbuf[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	ret = regmap_bulk_read(pcf2123->map, PCF2123_REG_SC, rxbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 				sizeof(rxbuf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (rxbuf[0] & OSC_HAS_STOPPED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		dev_info(dev, "clock was stopped. Time is not valid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	tm->tm_min = bcd2bin(rxbuf[1] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	tm->tm_wday = rxbuf[4] & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	tm->tm_year = bcd2bin(rxbuf[6]) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	dev_dbg(dev, "%s: tm is %ptR\n", __func__, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int pcf2123_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	u8 txbuf[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	dev_dbg(dev, "%s: tm is %ptR\n", __func__, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	/* Stop the counter first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	/* Set the new time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	txbuf[0] = bin2bcd(tm->tm_sec & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	txbuf[1] = bin2bcd(tm->tm_min & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	txbuf[2] = bin2bcd(tm->tm_hour & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	txbuf[3] = bin2bcd(tm->tm_mday & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	txbuf[4] = tm->tm_wday & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	txbuf[5] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	txbuf[6] = bin2bcd(tm->tm_year - 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	ret = regmap_bulk_write(pcf2123->map, PCF2123_REG_SC, txbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 				sizeof(txbuf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	/* Start the counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int pcf2123_rtc_alarm_irq_enable(struct device *dev, unsigned int en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	return regmap_update_bits(pcf2123->map, PCF2123_REG_CTRL2, CTRL2_AIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 				  en ? CTRL2_AIE : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int pcf2123_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	u8 rxbuf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	ret = regmap_bulk_read(pcf2123->map, PCF2123_REG_ALRM_MN, rxbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 				sizeof(rxbuf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	alm->time.tm_min = bcd2bin(rxbuf[0] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	alm->time.tm_hour = bcd2bin(rxbuf[1] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	alm->time.tm_mday = bcd2bin(rxbuf[2] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	alm->time.tm_wday = bcd2bin(rxbuf[3] & 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	dev_dbg(dev, "%s: alm is %ptR\n", __func__, &alm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	ret = regmap_read(pcf2123->map, PCF2123_REG_CTRL2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	alm->enabled = !!(val & CTRL2_AIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int pcf2123_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	u8 txbuf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	dev_dbg(dev, "%s: alm is %ptR\n", __func__, &alm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	/* Disable alarm interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	ret = regmap_update_bits(pcf2123->map, PCF2123_REG_CTRL2, CTRL2_AIE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	/* Ensure alarm flag is clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	ret = regmap_update_bits(pcf2123->map, PCF2123_REG_CTRL2, CTRL2_AF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	/* Set new alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	txbuf[0] = bin2bcd(alm->time.tm_min & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	txbuf[1] = bin2bcd(alm->time.tm_hour & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	txbuf[2] = bin2bcd(alm->time.tm_mday & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	txbuf[3] = ALRM_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	ret = regmap_bulk_write(pcf2123->map, PCF2123_REG_ALRM_MN, txbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 				sizeof(txbuf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	return pcf2123_rtc_alarm_irq_enable(dev, alm->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static irqreturn_t pcf2123_rtc_irq(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	struct mutex *lock = &pcf2123->rtc->ops_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	int ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	mutex_lock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	regmap_read(pcf2123->map, PCF2123_REG_CTRL2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	/* Alarm? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	if (val & CTRL2_AF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		/* Clear alarm flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		regmap_update_bits(pcf2123->map, PCF2123_REG_CTRL2, CTRL2_AF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		rtc_update_irq(pcf2123->rtc, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	mutex_unlock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int pcf2123_reset(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	struct pcf2123_data *pcf2123 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_SW_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	/* Stop the counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	dev_dbg(dev, "stopping RTC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	/* See if the counter was actually stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	dev_dbg(dev, "checking for presence of RTC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	ret = regmap_read(pcf2123->map, PCF2123_REG_CTRL1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	dev_dbg(dev, "received data from RTC (0x%08X)\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	if (!(val & CTRL1_STOP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	/* Start the counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	ret = regmap_write(pcf2123->map, PCF2123_REG_CTRL1, CTRL1_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const struct rtc_class_ops pcf2123_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	.read_time	= pcf2123_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	.set_time	= pcf2123_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	.read_offset	= pcf2123_read_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	.set_offset	= pcf2123_set_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	.read_alarm	= pcf2123_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	.set_alarm	= pcf2123_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	.alarm_irq_enable = pcf2123_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int pcf2123_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	struct rtc_time tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	struct pcf2123_data *pcf2123;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	pcf2123 = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 				GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	if (!pcf2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	dev_set_drvdata(&spi->dev, pcf2123);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	pcf2123->map = devm_regmap_init_spi(spi, &pcf2123_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	if (IS_ERR(pcf2123->map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		dev_err(&spi->dev, "regmap init failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		return PTR_ERR(pcf2123->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	ret = pcf2123_rtc_read_time(&spi->dev, &tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		ret = pcf2123_reset(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 			dev_err(&spi->dev, "chip not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	dev_info(&spi->dev, "spiclk %u KHz.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 			(spi->max_speed_hz + 500) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	/* Finalize the initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	rtc = devm_rtc_allocate_device(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	if (IS_ERR(rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		return PTR_ERR(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	pcf2123->rtc = rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	/* Register alarm irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	if (spi->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 				pcf2123_rtc_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 				IRQF_TRIGGER_LOW | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 				pcf2123_driver.driver.name, &spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 			device_init_wakeup(&spi->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 			dev_err(&spi->dev, "could not request irq.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	/* The PCF2123's alarm only has minute accuracy. Must add timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	 * support to this driver to generate interrupts more than once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	 * per minute.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	rtc->uie_unsupported = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	rtc->ops = &pcf2123_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	rtc->range_max = RTC_TIMESTAMP_END_2099;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	rtc->set_start_time = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	ret = rtc_register_device(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static const struct of_device_id pcf2123_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	{ .compatible = "nxp,pcf2123", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	{ .compatible = "microcrystal,rv2123", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	/* Deprecated, do not use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	{ .compatible = "nxp,rtc-pcf2123", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MODULE_DEVICE_TABLE(of, pcf2123_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static struct spi_driver pcf2123_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 			.name	= "rtc-pcf2123",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 			.of_match_table = of_match_ptr(pcf2123_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	.probe	= pcf2123_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) module_spi_driver(pcf2123_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MODULE_DESCRIPTION("NXP PCF2123 RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) MODULE_LICENSE("GPL");