^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Real Time Clock (RTC) Driver for i.MX53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2017 Beckhoff Automation GmbH & Co. KG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pm_wakeirq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SRTC_LPPDR_INIT 0x41736166 /* init for glitch detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SRTC_LPCR_EN_LP BIT(3) /* lp enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SRTC_LPCR_WAE BIT(4) /* lp wakeup alarm enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SRTC_LPCR_ALP BIT(7) /* lp alarm flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SRTC_LPCR_NSA BIT(11) /* lp non secure access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SRTC_LPCR_NVE BIT(14) /* lp non valid state exit bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SRTC_LPCR_IE BIT(15) /* lp init state exit bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SRTC_LPSR_ALP BIT(3) /* lp alarm flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SRTC_LPSR_NVES BIT(14) /* lp non-valid state exit status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SRTC_LPSR_IES BIT(15) /* lp init state exit status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SRTC_LPCR 0x10 /* LP Control Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SRTC_LPSR 0x14 /* LP Status Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SRTC_LPPDR 0x18 /* LP Power Supply Glitch Detector Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* max. number of retries to read registers, 120 was max during test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_READ_TIMEOUT 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct mxc_rtc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) spinlock_t lock; /* protects register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * This function does write synchronization for writes to the lp srtc block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * To take care of the asynchronous CKIL clock, all writes from the IP domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * will be synchronized to the CKIL domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * The caller should hold the pdata->lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static void mxc_rtc_sync_lp_locked(struct device *dev, void __iomem *ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Wait for 3 CKIL cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) const u32 count = readl(ioaddr + SRTC_LPSCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int timeout = REG_READ_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) while ((readl(ioaddr + SRTC_LPSCLR)) == count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (!--timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) dev_err_once(dev, "SRTC_LPSCLR stuck! Check your hw.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* This function is the RTC interrupt service routine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct device *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) void __iomem *ioaddr = pdata->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 lp_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 lp_cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) spin_lock_irqsave(&pdata->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (clk_enable(pdata->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) spin_unlock_irqrestore(&pdata->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) lp_status = readl(ioaddr + SRTC_LPSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) lp_cr = readl(ioaddr + SRTC_LPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* update irq data & counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (lp_status & SRTC_LPSR_ALP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (lp_cr & SRTC_LPCR_ALP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) rtc_update_irq(pdata->rtc, 1, RTC_AF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* disable further lp alarm interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Update interrupt enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) writel(lp_cr, ioaddr + SRTC_LPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* clear interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) writel(lp_status, ioaddr + SRTC_LPSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) mxc_rtc_sync_lp_locked(dev, ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) clk_disable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) spin_unlock_irqrestore(&pdata->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * Enable clk and aquire spinlock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @return 0 if successful; non-zero otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int mxc_rtc_lock(struct mxc_rtc_data *const pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) spin_lock_irq(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ret = clk_enable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) spin_unlock_irq(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int mxc_rtc_unlock(struct mxc_rtc_data *const pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) clk_disable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) spin_unlock_irq(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * This function reads the current RTC time into tm in Gregorian date.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @param tm contains the RTC time value upon return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @return 0 if successful; non-zero otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) const int clk_failed = clk_enable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (!clk_failed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) const time64_t now = readl(pdata->ioaddr + SRTC_LPSCMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) rtc_time64_to_tm(now, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) clk_disable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return clk_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * This function sets the internal RTC time based on tm in Gregorian date.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @param tm the time value to be set in the RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @return 0 if successful; non-zero otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) time64_t time = rtc_tm_to_time64(tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ret = mxc_rtc_lock(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) writel(time, pdata->ioaddr + SRTC_LPSCMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return mxc_rtc_unlock(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * This function reads the current alarm value into the passed in \b alrm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * argument. It updates the \b alrm's pending field value based on the whether
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * an alarm interrupt occurs or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * @param alrm contains the RTC alarm value upon return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * @return 0 if successful; non-zero otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) void __iomem *ioaddr = pdata->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ret = mxc_rtc_lock(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) rtc_time64_to_tm(readl(ioaddr + SRTC_LPSAR), &alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) alrm->pending = !!(readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_ALP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return mxc_rtc_unlock(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * Enable/Disable alarm interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * The caller should hold the pdata->lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void mxc_rtc_alarm_irq_enable_locked(struct mxc_rtc_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 lp_cr = readl(pdata->ioaddr + SRTC_LPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) lp_cr |= (SRTC_LPCR_ALP | SRTC_LPCR_WAE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) writel(lp_cr, pdata->ioaddr + SRTC_LPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int ret = mxc_rtc_lock(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) mxc_rtc_alarm_irq_enable_locked(pdata, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return mxc_rtc_unlock(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * This function sets the RTC alarm based on passed in alrm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @param alrm the alarm value to be set in the RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * @return 0 if successful; non-zero otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) const time64_t time = rtc_tm_to_time64(&alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int ret = mxc_rtc_lock(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) writel((u32)time, pdata->ioaddr + SRTC_LPSAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* clear alarm interrupt status bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) writel(SRTC_LPSR_ALP, pdata->ioaddr + SRTC_LPSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) mxc_rtc_alarm_irq_enable_locked(pdata, alrm->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) mxc_rtc_sync_lp_locked(dev, pdata->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) mxc_rtc_unlock(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const struct rtc_class_ops mxc_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .read_time = mxc_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .set_time = mxc_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .read_alarm = mxc_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .set_alarm = mxc_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .alarm_irq_enable = mxc_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int mxc_rtc_wait_for_flag(void __iomem *ioaddr, int flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned int timeout = REG_READ_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) while (!(readl(ioaddr) & flag)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (!--timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int mxc_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct mxc_rtc_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) pdata->ioaddr = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (IS_ERR(pdata->ioaddr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return PTR_ERR(pdata->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ioaddr = pdata->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) pdata->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (IS_ERR(pdata->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_err(&pdev->dev, "unable to get rtc clock!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return PTR_ERR(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) spin_lock_init(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pdata->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (pdata->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return pdata->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = dev_pm_set_wake_irq(&pdev->dev, pdata->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev_err(&pdev->dev, "failed to enable irq wake\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ret = clk_prepare_enable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* initialize glitch detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) writel(SRTC_LPPDR_INIT, ioaddr + SRTC_LPPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* clear lp interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* move out of init state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) writel((SRTC_LPCR_IE | SRTC_LPCR_NSA), ioaddr + SRTC_LPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ret = mxc_rtc_wait_for_flag(ioaddr + SRTC_LPSR, SRTC_LPSR_IES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_err(&pdev->dev, "Timeout waiting for SRTC_LPSR_IES\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) clk_disable_unprepare(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* move out of non-valid state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) writel((SRTC_LPCR_IE | SRTC_LPCR_NVE | SRTC_LPCR_NSA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) SRTC_LPCR_EN_LP), ioaddr + SRTC_LPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ret = mxc_rtc_wait_for_flag(ioaddr + SRTC_LPSR, SRTC_LPSR_NVES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dev_err(&pdev->dev, "Timeout waiting for SRTC_LPSR_NVES\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) clk_disable_unprepare(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (IS_ERR(pdata->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return PTR_ERR(pdata->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) pdata->rtc->ops = &mxc_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) pdata->rtc->range_max = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) clk_disable(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) platform_set_drvdata(pdev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pdev->name, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dev_err(&pdev->dev, "interrupt not available.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) clk_unprepare(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ret = rtc_register_device(pdata->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) clk_unprepare(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static int mxc_rtc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct mxc_rtc_data *pdata = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) clk_disable_unprepare(pdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const struct of_device_id mxc_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { .compatible = "fsl,imx53-rtc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MODULE_DEVICE_TABLE(of, mxc_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static struct platform_driver mxc_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .name = "mxc_rtc_v2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .of_match_table = mxc_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .probe = mxc_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .remove = mxc_rtc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) module_platform_driver(mxc_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) MODULE_AUTHOR("Freescale Semiconductor, Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MODULE_DESCRIPTION("Real Time Clock (RTC) Driver for i.MX53");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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