^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pm_wakeirq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RTC_INPUT_CLK_32768HZ (0x00 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RTC_INPUT_CLK_32000HZ (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RTC_INPUT_CLK_38400HZ (0x02 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RTC_SW_BIT (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RTC_ALM_BIT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RTC_1HZ_BIT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RTC_2HZ_BIT (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RTC_SAM0_BIT (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RTC_SAM1_BIT (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RTC_SAM2_BIT (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RTC_SAM3_BIT (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RTC_SAM4_BIT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RTC_SAM5_BIT (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RTC_SAM6_BIT (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RTC_SAM7_BIT (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PIT_ALL_ON (RTC_2HZ_BIT | RTC_SAM0_BIT | RTC_SAM1_BIT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) RTC_SAM2_BIT | RTC_SAM3_BIT | RTC_SAM4_BIT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) RTC_SAM5_BIT | RTC_SAM6_BIT | RTC_SAM7_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RTC_ENABLE_BIT (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MAX_PIE_NUM 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MAX_PIE_FREQ 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MXC_RTC_TIME 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MXC_RTC_ALARM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RTC_HOURMIN 0x00 /* 32bit rtc hour/min counter reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RTC_SECOND 0x04 /* 32bit rtc seconds counter reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RTC_ALRM_HM 0x08 /* 32bit rtc alarm hour/min reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RTC_ALRM_SEC 0x0C /* 32bit rtc alarm seconds reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RTC_RTCCTL 0x10 /* 32bit rtc control reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RTC_RTCISR 0x14 /* 32bit rtc interrupt status reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RTC_RTCIENR 0x18 /* 32bit rtc interrupt enable reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RTC_STPWCH 0x1C /* 32bit rtc stopwatch min reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RTC_DAYR 0x20 /* 32bit rtc days counter reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RTC_DAYALARM 0x24 /* 32bit rtc day alarm reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RTC_TEST1 0x28 /* 32bit rtc test reg 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RTC_TEST2 0x2C /* 32bit rtc test reg 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RTC_TEST3 0x30 /* 32bit rtc test reg 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) enum imx_rtc_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) IMX1_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) IMX21_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct rtc_plat_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct clk *clk_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct clk *clk_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct rtc_time g_rtc_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) enum imx_rtc_type devtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const struct platform_device_id imx_rtc_devtype[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .name = "imx1-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .driver_data = IMX1_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .name = "imx21-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .driver_data = IMX21_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MODULE_DEVICE_TABLE(platform, imx_rtc_devtype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static const struct of_device_id imx_rtc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { .compatible = "fsl,imx1-rtc", .data = (const void *)IMX1_RTC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { .compatible = "fsl,imx21-rtc", .data = (const void *)IMX21_RTC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MODULE_DEVICE_TABLE(of, imx_rtc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static inline int is_imx1_rtc(struct rtc_plat_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return data->devtype == IMX1_RTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * This function is used to obtain the RTC time or the alarm value in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * second.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static time64_t get_alarm_or_time(struct device *dev, int time_alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct rtc_plat_data *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void __iomem *ioaddr = pdata->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 day = 0, hr = 0, min = 0, sec = 0, hr_min = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) switch (time_alarm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) case MXC_RTC_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) day = readw(ioaddr + RTC_DAYR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) hr_min = readw(ioaddr + RTC_HOURMIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) sec = readw(ioaddr + RTC_SECOND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case MXC_RTC_ALARM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) day = readw(ioaddr + RTC_DAYALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) hr_min = readw(ioaddr + RTC_ALRM_HM) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) sec = readw(ioaddr + RTC_ALRM_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) hr = hr_min >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) min = hr_min & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return ((((time64_t)day * 24 + hr) * 60) + min) * 60 + sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * This function sets the RTC alarm value or the time value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void set_alarm_or_time(struct device *dev, int time_alarm, time64_t time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 tod, day, hr, min, sec, temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct rtc_plat_data *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) void __iomem *ioaddr = pdata->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) day = div_s64_rem(time, 86400, &tod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* time is within a day now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) hr = tod / 3600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) tod -= hr * 3600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* time is within an hour now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) min = tod / 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) sec = tod - min * 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) temp = (hr << 8) + min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) switch (time_alarm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) case MXC_RTC_TIME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) writew(day, ioaddr + RTC_DAYR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) writew(sec, ioaddr + RTC_SECOND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) writew(temp, ioaddr + RTC_HOURMIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) case MXC_RTC_ALARM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) writew(day, ioaddr + RTC_DAYALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) writew(sec, ioaddr + RTC_ALRM_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) writew(temp, ioaddr + RTC_ALRM_HM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * This function updates the RTC alarm registers and then clears all the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * interrupt status bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void rtc_update_alarm(struct device *dev, struct rtc_time *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) time64_t time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct rtc_plat_data *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) void __iomem *ioaddr = pdata->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) time = rtc_tm_to_time64(alrm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* clear all the interrupt status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) writew(readw(ioaddr + RTC_RTCISR), ioaddr + RTC_RTCISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) set_alarm_or_time(dev, MXC_RTC_ALARM, time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void mxc_rtc_irq_enable(struct device *dev, unsigned int bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct rtc_plat_data *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) void __iomem *ioaddr = pdata->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) reg = readw(ioaddr + RTC_RTCIENR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) reg |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) reg &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) writew(reg, ioaddr + RTC_RTCIENR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* This function is the RTC interrupt service routine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct platform_device *pdev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct rtc_plat_data *pdata = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) void __iomem *ioaddr = pdata->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 events = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) spin_lock_irqsave(&pdata->rtc->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) status = readw(ioaddr + RTC_RTCISR) & readw(ioaddr + RTC_RTCIENR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* clear interrupt sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) writew(status, ioaddr + RTC_RTCISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* update irq data & counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (status & RTC_ALM_BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) events |= (RTC_AF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* RTC alarm should be one-shot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) mxc_rtc_irq_enable(&pdev->dev, RTC_ALM_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (status & PIT_ALL_ON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) events |= (RTC_PF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) rtc_update_irq(pdata->rtc, 1, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) spin_unlock_irqrestore(&pdata->rtc->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mxc_rtc_irq_enable(dev, RTC_ALM_BIT, enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * This function reads the current RTC time into tm in Gregorian date.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) time64_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Avoid roll-over from reading the different registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) val = get_alarm_or_time(dev, MXC_RTC_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) } while (val != get_alarm_or_time(dev, MXC_RTC_TIME));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) rtc_time64_to_tm(val, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * This function sets the internal RTC time based on tm in Gregorian date.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) time64_t time = rtc_tm_to_time64(tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Avoid roll-over from reading the different registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) set_alarm_or_time(dev, MXC_RTC_TIME, time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) } while (time != get_alarm_or_time(dev, MXC_RTC_TIME));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * This function reads the current alarm value into the passed in 'alrm'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * argument. It updates the alrm's pending field value based on the whether
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * an alarm interrupt occurs or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct rtc_plat_data *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) void __iomem *ioaddr = pdata->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) rtc_time64_to_tm(get_alarm_or_time(dev, MXC_RTC_ALARM), &alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) alrm->pending = ((readw(ioaddr + RTC_RTCISR) & RTC_ALM_BIT)) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * This function sets the RTC alarm based on passed in alrm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct rtc_plat_data *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) rtc_update_alarm(dev, &alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) memcpy(&pdata->g_rtc_alarm, &alrm->time, sizeof(struct rtc_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) mxc_rtc_irq_enable(dev, RTC_ALM_BIT, alrm->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* RTC layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const struct rtc_class_ops mxc_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .read_time = mxc_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .set_time = mxc_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .read_alarm = mxc_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .set_alarm = mxc_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .alarm_irq_enable = mxc_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static void mxc_rtc_action(void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct rtc_plat_data *pdata = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) clk_disable_unprepare(pdata->clk_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) clk_disable_unprepare(pdata->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int mxc_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct rtc_plat_data *pdata = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) of_id = of_match_device(imx_rtc_dt_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pdata->devtype = (enum imx_rtc_type)of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) pdata->devtype = pdev->id_entry->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) pdata->ioaddr = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (IS_ERR(pdata->ioaddr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return PTR_ERR(pdata->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (IS_ERR(rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return PTR_ERR(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) pdata->rtc = rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) rtc->ops = &mxc_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (is_imx1_rtc(pdata)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct rtc_time tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* 9bit days + hours minutes seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) rtc->range_max = (1 << 9) * 86400 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * Set the start date as beginning of the current year. This can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * be overridden using device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) rtc_time64_to_tm(ktime_get_real_seconds(), &tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) rtc->start_secs = mktime64(tm.tm_year, 1, 1, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) rtc->set_start_time = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* 16bit days + hours minutes seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) rtc->range_max = (1 << 16) * 86400ULL - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) pdata->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (IS_ERR(pdata->clk_ipg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dev_err(&pdev->dev, "unable to get ipg clock!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return PTR_ERR(pdata->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ret = clk_prepare_enable(pdata->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) pdata->clk_ref = devm_clk_get(&pdev->dev, "ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (IS_ERR(pdata->clk_ref)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) clk_disable_unprepare(pdata->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_err(&pdev->dev, "unable to get ref clock!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return PTR_ERR(pdata->clk_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ret = clk_prepare_enable(pdata->clk_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) clk_disable_unprepare(pdata->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ret = devm_add_action_or_reset(&pdev->dev, mxc_rtc_action, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) rate = clk_get_rate(pdata->clk_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (rate == 32768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) reg = RTC_INPUT_CLK_32768HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) else if (rate == 32000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) reg = RTC_INPUT_CLK_32000HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) else if (rate == 38400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) reg = RTC_INPUT_CLK_38400HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dev_err(&pdev->dev, "rtc clock is not valid (%lu)\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) reg |= RTC_ENABLE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) writew(reg, (pdata->ioaddr + RTC_RTCCTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (((readw(pdata->ioaddr + RTC_RTCCTL)) & RTC_ENABLE_BIT) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dev_err(&pdev->dev, "hardware module can't be enabled!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) platform_set_drvdata(pdev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Configure and enable the RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) pdata->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (pdata->irq >= 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) IRQF_SHARED, pdev->name, pdev) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_warn(&pdev->dev, "interrupt not available.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) pdata->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (pdata->irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ret = dev_pm_set_wake_irq(&pdev->dev, pdata->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev_err(&pdev->dev, "failed to enable irq wake\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret = rtc_register_device(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static struct platform_driver mxc_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .name = "mxc_rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .of_match_table = of_match_ptr(imx_rtc_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .id_table = imx_rtc_devtype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .probe = mxc_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) module_platform_driver(mxc_rtc_driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MODULE_DESCRIPTION("RTC driver for Freescale MXC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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