^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for MediaTek SoC based RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MTK_RTC_DEV KBUILD_MODNAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MTK_RTC_PWRCHK1 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RTC_PWRCHK1_MAGIC 0xc6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MTK_RTC_PWRCHK2 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RTC_PWRCHK2_MAGIC 0x9a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MTK_RTC_KEY 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RTC_KEY_MAGIC 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MTK_RTC_PROT1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RTC_PROT1_MAGIC 0xa3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MTK_RTC_PROT2 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RTC_PROT2_MAGIC 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MTK_RTC_PROT3 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RTC_PROT3_MAGIC 0x67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MTK_RTC_PROT4 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RTC_PROT4_MAGIC 0xd2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MTK_RTC_CTL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RTC_RC_STOP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MTK_RTC_DEBNCE 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RTC_DEBNCE_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MTK_RTC_INT 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RTC_INT_AL_STA BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Ranges from 0x40 to 0x78 provide RTC time setup for year, month,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * day of month, day of week, hour, minute and second.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MTK_RTC_TREG(_t, _f) (0x40 + (0x4 * (_f)) + ((_t) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MTK_RTC_AL_CTL 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RTC_AL_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RTC_AL_ALL GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * The offset is used in the translation for the year between in struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * rtc_time and in hardware register MTK_RTC_TREG(x,MTK_YEA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MTK_RTC_TM_YR_OFFSET 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * The lowest value for the valid tm_year. RTC hardware would take incorrectly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * tm_year 100 as not a leap year and thus it is also required being excluded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * from the valid options.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MTK_RTC_TM_YR_L (MTK_RTC_TM_YR_OFFSET + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * The most year the RTC can hold is 99 and the next to 99 in year register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * would be wraparound to 0, for MT7622.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MTK_RTC_HW_YR_LIMIT 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* The highest value for the valid tm_year */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MTK_RTC_TM_YR_H (MTK_RTC_TM_YR_OFFSET + MTK_RTC_HW_YR_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Simple macro helps to check whether the hardware supports the tm_year */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MTK_RTC_TM_YR_VALID(_y) ((_y) >= MTK_RTC_TM_YR_L && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) (_y) <= MTK_RTC_TM_YR_H)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Types of the function the RTC provides are time counter and alarm. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MTK_TC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MTK_AL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Indexes are used for the pointer to relevant registers in MTK_RTC_TREG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MTK_YEA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MTK_MON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MTK_DOM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MTK_DOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MTK_HOU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MTK_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MTK_SEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct mtk_rtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void mtk_w32(struct mtk_rtc *rtc, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) writel_relaxed(val, rtc->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static u32 mtk_r32(struct mtk_rtc *rtc, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return readl_relaxed(rtc->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void mtk_rmw(struct mtk_rtc *rtc, u32 reg, u32 mask, u32 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) val = mtk_r32(rtc, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) val |= set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) mtk_w32(rtc, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void mtk_set(struct mtk_rtc *rtc, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mtk_rmw(rtc, reg, 0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void mtk_clr(struct mtk_rtc *rtc, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) mtk_rmw(rtc, reg, val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void mtk_rtc_hw_init(struct mtk_rtc *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* The setup of the init sequence is for allowing RTC got to work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mtk_w32(hw, MTK_RTC_PWRCHK1, RTC_PWRCHK1_MAGIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) mtk_w32(hw, MTK_RTC_PWRCHK2, RTC_PWRCHK2_MAGIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) mtk_w32(hw, MTK_RTC_KEY, RTC_KEY_MAGIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) mtk_w32(hw, MTK_RTC_PROT1, RTC_PROT1_MAGIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) mtk_w32(hw, MTK_RTC_PROT2, RTC_PROT2_MAGIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) mtk_w32(hw, MTK_RTC_PROT3, RTC_PROT3_MAGIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) mtk_w32(hw, MTK_RTC_PROT4, RTC_PROT4_MAGIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) mtk_rmw(hw, MTK_RTC_DEBNCE, RTC_DEBNCE_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) mtk_clr(hw, MTK_RTC_CTL, RTC_RC_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static void mtk_rtc_get_alarm_or_time(struct mtk_rtc *hw, struct rtc_time *tm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int time_alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 year, mon, mday, wday, hour, min, sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Read again until the field of the second is not changed which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * ensures all fields in the consistent state. Note that MTK_SEC must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * be read first. In this way, it guarantees the others remain not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * changed when the results for two MTK_SEC consecutive reads are same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) sec = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) min = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_MIN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) hour = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_HOU));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) wday = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_DOW));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) mday = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_DOM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) mon = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_MON));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) year = mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_YEA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) } while (sec != mtk_r32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) tm->tm_sec = sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) tm->tm_min = min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) tm->tm_hour = hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) tm->tm_wday = wday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) tm->tm_mday = mday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) tm->tm_mon = mon - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Rebase to the absolute year which userspace queries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) tm->tm_year = year + MTK_RTC_TM_YR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void mtk_rtc_set_alarm_or_time(struct mtk_rtc *hw, struct rtc_time *tm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int time_alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Rebase to the relative year which RTC hardware requires */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) year = tm->tm_year - MTK_RTC_TM_YR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_YEA), year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_MON), tm->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_DOW), tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_DOM), tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_HOU), tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_MIN), tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mtk_w32(hw, MTK_RTC_TREG(time_alarm, MTK_SEC), tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static irqreturn_t mtk_rtc_alarmirq(int irq, void *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct mtk_rtc *hw = (struct mtk_rtc *)id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 irq_sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) irq_sta = mtk_r32(hw, MTK_RTC_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (irq_sta & RTC_INT_AL_STA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Stop alarm also implicitly disables the alarm interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) mtk_w32(hw, MTK_RTC_AL_CTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) rtc_update_irq(hw->rtc, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Ack alarm interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) mtk_w32(hw, MTK_RTC_INT, RTC_INT_AL_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int mtk_rtc_gettime(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct mtk_rtc *hw = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) mtk_rtc_get_alarm_or_time(hw, tm, MTK_TC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int mtk_rtc_settime(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct mtk_rtc *hw = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (!MTK_RTC_TM_YR_VALID(tm->tm_year))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Stop time counter before setting a new one*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) mtk_set(hw, MTK_RTC_CTL, RTC_RC_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mtk_rtc_set_alarm_or_time(hw, tm, MTK_TC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Restart the time counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) mtk_clr(hw, MTK_RTC_CTL, RTC_RC_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int mtk_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct mtk_rtc *hw = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct rtc_time *alrm_tm = &wkalrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) mtk_rtc_get_alarm_or_time(hw, alrm_tm, MTK_AL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) wkalrm->enabled = !!(mtk_r32(hw, MTK_RTC_AL_CTL) & RTC_AL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) wkalrm->pending = !!(mtk_r32(hw, MTK_RTC_INT) & RTC_INT_AL_STA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int mtk_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct mtk_rtc *hw = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct rtc_time *alrm_tm = &wkalrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (!MTK_RTC_TM_YR_VALID(alrm_tm->tm_year))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * Stop the alarm also implicitly including disables interrupt before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * setting a new one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) mtk_clr(hw, MTK_RTC_AL_CTL, RTC_AL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * Avoid contention between mtk_rtc_setalarm and IRQ handler so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * disabling the interrupt and awaiting for pending IRQ handler to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) synchronize_irq(hw->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mtk_rtc_set_alarm_or_time(hw, alrm_tm, MTK_AL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Restart the alarm with the new setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) mtk_w32(hw, MTK_RTC_AL_CTL, RTC_AL_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const struct rtc_class_ops mtk_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .read_time = mtk_rtc_gettime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .set_time = mtk_rtc_settime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .read_alarm = mtk_rtc_getalarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .set_alarm = mtk_rtc_setalarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const struct of_device_id mtk_rtc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { .compatible = "mediatek,mt7622-rtc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { .compatible = "mediatek,soc-rtc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MODULE_DEVICE_TABLE(of, mtk_rtc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int mtk_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct mtk_rtc *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (!hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) platform_set_drvdata(pdev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) hw->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (IS_ERR(hw->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return PTR_ERR(hw->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) hw->clk = devm_clk_get(&pdev->dev, "rtc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (IS_ERR(hw->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_err(&pdev->dev, "No clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return PTR_ERR(hw->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ret = clk_prepare_enable(hw->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) hw->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (hw->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ret = hw->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ret = devm_request_irq(&pdev->dev, hw->irq, mtk_rtc_alarmirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 0, dev_name(&pdev->dev), hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dev_err(&pdev->dev, "Can't request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) mtk_rtc_hw_init(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) device_init_wakeup(&pdev->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) hw->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) &mtk_rtc_ops, THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (IS_ERR(hw->rtc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ret = PTR_ERR(hw->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_err(&pdev->dev, "Unable to register device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) clk_disable_unprepare(hw->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int mtk_rtc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct mtk_rtc *hw = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) clk_disable_unprepare(hw->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int mtk_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct mtk_rtc *hw = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) enable_irq_wake(hw->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int mtk_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct mtk_rtc *hw = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) disable_irq_wake(hw->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static SIMPLE_DEV_PM_OPS(mtk_rtc_pm_ops, mtk_rtc_suspend, mtk_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define MTK_RTC_PM_OPS (&mtk_rtc_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #else /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define MTK_RTC_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #endif /* CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static struct platform_driver mtk_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .probe = mtk_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .remove = mtk_rtc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .name = MTK_RTC_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .of_match_table = mtk_rtc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .pm = MTK_RTC_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) module_platform_driver(mtk_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) MODULE_DESCRIPTION("MediaTek SoC based RTC Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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