^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014-2015 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Tianping.Fang <tianping.fang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mfd/mt6397/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/mt6397/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) ret = regmap_write(rtc->regmap, rtc->addr_base + rtc->data->wrtgr, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ret = regmap_read_poll_timeout(rtc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) rtc->addr_base + RTC_BBPU, data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) !(data & RTC_BBPU_CBUSY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MTK_RTC_POLL_DELAY_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MTK_RTC_POLL_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) dev_err(rtc->rtc_dev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) "failed to write WRTGR: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static irqreturn_t mtk_rtc_irq_handler_thread(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct mt6397_rtc *rtc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 irqsta, irqen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_STA, &irqsta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if ((ret >= 0) && (irqsta & RTC_IRQ_STA_AL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) irqen = irqsta & ~RTC_IRQ_EN_AL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) mutex_lock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (regmap_write(rtc->regmap, rtc->addr_base + RTC_IRQ_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) irqen) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) mtk_rtc_write_trigger(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) mutex_unlock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int __mtk_rtc_read_time(struct mt6397_rtc *rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct rtc_time *tm, int *sec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u16 data[RTC_OFFSET_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) mutex_lock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) data, RTC_OFFSET_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) tm->tm_sec = data[RTC_OFFSET_SEC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) tm->tm_min = data[RTC_OFFSET_MIN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) tm->tm_hour = data[RTC_OFFSET_HOUR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) tm->tm_mday = data[RTC_OFFSET_DOM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) tm->tm_mon = data[RTC_OFFSET_MTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) tm->tm_year = data[RTC_OFFSET_YEAR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC, sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) mutex_unlock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int mtk_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) time64_t time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct mt6397_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int days, sec, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = __mtk_rtc_read_time(rtc, tm, &sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) } while (sec < tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* HW register use 7 bits to store year data, minus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * RTC_MIN_YEAR_OFFSET before write year data to register, and plus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * RTC_MIN_YEAR_OFFSET back after read year from register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) tm->tm_year += RTC_MIN_YEAR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* HW register start mon from one, but tm_mon start from zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) tm->tm_mon--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) time = rtc_tm_to_time64(tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* rtc_tm_to_time64 covert Gregorian date to seconds since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * 01-01-1970 00:00:00, and this date is Thursday.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) days = div_s64(time, 86400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) tm->tm_wday = (days + 4) % 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int mtk_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct mt6397_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u16 data[RTC_OFFSET_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) tm->tm_year -= RTC_MIN_YEAR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) tm->tm_mon++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) data[RTC_OFFSET_SEC] = tm->tm_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) data[RTC_OFFSET_MIN] = tm->tm_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) data[RTC_OFFSET_HOUR] = tm->tm_hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) data[RTC_OFFSET_DOM] = tm->tm_mday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) data[RTC_OFFSET_MTH] = tm->tm_mon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) data[RTC_OFFSET_YEAR] = tm->tm_year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) mutex_lock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ret = regmap_bulk_write(rtc->regmap, rtc->addr_base + RTC_TC_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) data, RTC_OFFSET_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Time register write to hardware after call trigger function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ret = mtk_rtc_write_trigger(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) mutex_unlock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int mtk_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct rtc_time *tm = &alm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct mt6397_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 irqen, pdn2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u16 data[RTC_OFFSET_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) mutex_lock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_EN, &irqen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) goto err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_PDN2, &pdn2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) goto err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_AL_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) data, RTC_OFFSET_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) goto err_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) alm->enabled = !!(irqen & RTC_IRQ_EN_AL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) alm->pending = !!(pdn2 & RTC_PDN2_PWRON_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) mutex_unlock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) tm->tm_sec = data[RTC_OFFSET_SEC] & RTC_AL_SEC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) tm->tm_min = data[RTC_OFFSET_MIN] & RTC_AL_MIN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) tm->tm_hour = data[RTC_OFFSET_HOUR] & RTC_AL_HOU_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) tm->tm_mday = data[RTC_OFFSET_DOM] & RTC_AL_DOM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) tm->tm_mon = data[RTC_OFFSET_MTH] & RTC_AL_MTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) tm->tm_year = data[RTC_OFFSET_YEAR] & RTC_AL_YEA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) tm->tm_year += RTC_MIN_YEAR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) tm->tm_mon--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) err_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) mutex_unlock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int mtk_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct rtc_time *tm = &alm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct mt6397_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u16 data[RTC_OFFSET_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) tm->tm_year -= RTC_MIN_YEAR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) tm->tm_mon++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) mutex_lock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_AL_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) data, RTC_OFFSET_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) data[RTC_OFFSET_SEC] = ((data[RTC_OFFSET_SEC] & ~(RTC_AL_SEC_MASK)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) (tm->tm_sec & RTC_AL_SEC_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) data[RTC_OFFSET_MIN] = ((data[RTC_OFFSET_MIN] & ~(RTC_AL_MIN_MASK)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) (tm->tm_min & RTC_AL_MIN_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) data[RTC_OFFSET_HOUR] = ((data[RTC_OFFSET_HOUR] & ~(RTC_AL_HOU_MASK)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) (tm->tm_hour & RTC_AL_HOU_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) data[RTC_OFFSET_DOM] = ((data[RTC_OFFSET_DOM] & ~(RTC_AL_DOM_MASK)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) (tm->tm_mday & RTC_AL_DOM_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) data[RTC_OFFSET_MTH] = ((data[RTC_OFFSET_MTH] & ~(RTC_AL_MTH_MASK)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) (tm->tm_mon & RTC_AL_MTH_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) data[RTC_OFFSET_YEAR] = ((data[RTC_OFFSET_YEAR] & ~(RTC_AL_YEA_MASK)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) (tm->tm_year & RTC_AL_YEA_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (alm->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = regmap_bulk_write(rtc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) rtc->addr_base + RTC_AL_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) data, RTC_OFFSET_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_AL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) RTC_AL_MASK_DOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ret = regmap_update_bits(rtc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) rtc->addr_base + RTC_IRQ_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) RTC_IRQ_EN_ONESHOT_AL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) RTC_IRQ_EN_ONESHOT_AL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = regmap_update_bits(rtc->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) rtc->addr_base + RTC_IRQ_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) RTC_IRQ_EN_ONESHOT_AL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* All alarm time register write to hardware after calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * mtk_rtc_write_trigger. This can avoid race condition if alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * occur happen during writing alarm time register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ret = mtk_rtc_write_trigger(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) mutex_unlock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const struct rtc_class_ops mtk_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .read_time = mtk_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .set_time = mtk_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .read_alarm = mtk_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .set_alarm = mtk_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int mtk_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct mt6397_chip *mt6397_chip = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct mt6397_rtc *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) rtc = devm_kzalloc(&pdev->dev, sizeof(struct mt6397_rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (!rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) rtc->addr_base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) rtc->data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) rtc->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (rtc->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return rtc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) rtc->regmap = mt6397_chip->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mutex_init(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) platform_set_drvdata(pdev, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (IS_ERR(rtc->rtc_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return PTR_ERR(rtc->rtc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = devm_request_threaded_irq(&pdev->dev, rtc->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) mtk_rtc_irq_handler_thread,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "mt6397-rtc", rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) rtc->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) rtc->rtc_dev->ops = &mtk_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return rtc_register_device(rtc->rtc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int mt6397_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct mt6397_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) enable_irq_wake(rtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int mt6397_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct mt6397_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) disable_irq_wake(rtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_rtc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mt6397_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const struct mtk_rtc_data mt6358_rtc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .wrtgr = RTC_WRTGR_MT6358,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const struct mtk_rtc_data mt6397_rtc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .wrtgr = RTC_WRTGR_MT6397,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const struct of_device_id mt6397_rtc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { .compatible = "mediatek,mt6323-rtc", .data = &mt6397_rtc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { .compatible = "mediatek,mt6358-rtc", .data = &mt6358_rtc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { .compatible = "mediatek,mt6397-rtc", .data = &mt6397_rtc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MODULE_DEVICE_TABLE(of, mt6397_rtc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static struct platform_driver mtk_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .name = "mt6397-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .of_match_table = mt6397_rtc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .pm = &mt6397_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .probe = mtk_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) module_platform_driver(mtk_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MODULE_AUTHOR("Tianping Fang <tianping.fang@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MODULE_DESCRIPTION("RTC Driver for MediaTek MT6397 PMIC");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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