Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * RTC driver for the interal RTC block in the Amlogic Meson6, Meson8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Meson8b and Meson8m2 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * The RTC is split in to two parts, the AHB front end and a simple serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * connection to the actual registers. This driver manages both parts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright (c) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Copyright (c) 2015 Ben Dooks <ben.dooks@codethink.co.uk> for Codethink Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Based on origin by Carlo Caione <carlo@endlessm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* registers accessed from cpu bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define RTC_ADDR0				0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	#define RTC_ADDR0_LINE_SCLK		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	#define RTC_ADDR0_LINE_SEN		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	#define RTC_ADDR0_LINE_SDI		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	#define RTC_ADDR0_START_SER		BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	#define RTC_ADDR0_WAIT_SER		BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	#define RTC_ADDR0_DATA			GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define RTC_ADDR1				0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	#define RTC_ADDR1_SDO			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	#define RTC_ADDR1_S_READY		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define RTC_ADDR2				0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define RTC_ADDR3				0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define RTC_REG4				0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	#define RTC_REG4_STATIC_VALUE		GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* rtc registers accessed via rtc-serial interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define RTC_COUNTER		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define RTC_SEC_ADJ		(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define RTC_REGMEM_0		(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define RTC_REGMEM_1		(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define RTC_REGMEM_2		(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define RTC_REGMEM_3		(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define RTC_ADDR_BITS		(3)	/* number of address bits to send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define RTC_DATA_BITS		(32)	/* number of data bits to tx/rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define MESON_STATIC_BIAS_CUR	(0x5 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define MESON_STATIC_VOLTAGE	(0x3 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define MESON_STATIC_DEFAULT    (MESON_STATIC_BIAS_CUR | MESON_STATIC_VOLTAGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) struct meson_rtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct rtc_device	*rtc;		/* rtc device we created */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct device		*dev;		/* device we bound from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct reset_control	*reset;		/* reset source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct regulator	*vdd;		/* voltage input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct regmap		*peripheral;	/* peripheral registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct regmap		*serial;	/* serial registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static const struct regmap_config meson_rtc_peripheral_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	.name		= "peripheral-registers",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	.reg_bits	= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	.val_bits	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	.reg_stride	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	.max_register	= RTC_REG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	.fast_io	= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) /* RTC front-end serialiser controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static void meson_rtc_sclk_pulse(struct meson_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SCLK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			   RTC_ADDR0_LINE_SCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static void meson_rtc_send_bit(struct meson_rtc *rtc, unsigned int bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SDI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			   bit ? RTC_ADDR0_LINE_SDI : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	meson_rtc_sclk_pulse(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static void meson_rtc_send_bits(struct meson_rtc *rtc, u32 data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 				unsigned int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	u32 bit = 1 << (nr - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	while (bit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		meson_rtc_send_bit(rtc, data & bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		bit >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void meson_rtc_set_dir(struct meson_rtc *rtc, u32 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SDI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	meson_rtc_send_bit(rtc, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SDI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static u32 meson_rtc_get_data(struct meson_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	u32 tmp, val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	for (bit = 0; bit < RTC_DATA_BITS; bit++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		meson_rtc_sclk_pulse(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		val <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		regmap_read(rtc->peripheral, RTC_ADDR1, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		val |= tmp & RTC_ADDR1_SDO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int meson_rtc_get_bus(struct meson_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	int ret, retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	/* prepare bus for transfers, set all lines low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	val = RTC_ADDR0_LINE_SDI | RTC_ADDR0_LINE_SEN | RTC_ADDR0_LINE_SCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	regmap_update_bits(rtc->peripheral, RTC_ADDR0, val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	for (retries = 0; retries < 3; retries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		/* wait for the bus to be ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		if (!regmap_read_poll_timeout(rtc->peripheral, RTC_ADDR1, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 					      val & RTC_ADDR1_S_READY, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 					      10000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		dev_warn(rtc->dev, "failed to get bus, resetting RTC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		ret = reset_control_reset(rtc->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	dev_err(rtc->dev, "bus is not ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int meson_rtc_serial_bus_reg_read(void *context, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 					 unsigned int *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct meson_rtc *rtc = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	ret = meson_rtc_get_bus(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			   RTC_ADDR0_LINE_SEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	meson_rtc_send_bits(rtc, reg, RTC_ADDR_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	meson_rtc_set_dir(rtc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	*data = meson_rtc_get_data(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int meson_rtc_serial_bus_reg_write(void *context, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 					  unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct meson_rtc *rtc = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	ret = meson_rtc_get_bus(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			   RTC_ADDR0_LINE_SEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	meson_rtc_send_bits(rtc, data, RTC_DATA_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	meson_rtc_send_bits(rtc, reg, RTC_ADDR_BITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	meson_rtc_set_dir(rtc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const struct regmap_bus meson_rtc_serial_bus = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.reg_read	= meson_rtc_serial_bus_reg_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.reg_write	= meson_rtc_serial_bus_reg_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const struct regmap_config meson_rtc_serial_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.name		= "serial-registers",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.reg_bits	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.reg_stride	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.val_bits	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.max_register	= RTC_REGMEM_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.fast_io	= false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int meson_rtc_write_static(struct meson_rtc *rtc, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	regmap_write(rtc->peripheral, RTC_REG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		     FIELD_PREP(RTC_REG4_STATIC_VALUE, (data >> 8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	/* write the static value and start the auto serializer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	tmp = FIELD_PREP(RTC_ADDR0_DATA, (data & 0xff)) | RTC_ADDR0_START_SER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	regmap_update_bits(rtc->peripheral, RTC_ADDR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			   RTC_ADDR0_DATA | RTC_ADDR0_START_SER, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/* wait for the auto serializer to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	return regmap_read_poll_timeout(rtc->peripheral, RTC_REG4, tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 					!(tmp & RTC_ADDR0_WAIT_SER), 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 					10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* RTC interface layer functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int meson_rtc_gettime(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	struct meson_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	u32 time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	ret = regmap_read(rtc->serial, RTC_COUNTER, &time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		rtc_time64_to_tm(time, tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int meson_rtc_settime(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	struct meson_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	return regmap_write(rtc->serial, RTC_COUNTER, rtc_tm_to_time64(tm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const struct rtc_class_ops meson_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	.read_time	= meson_rtc_gettime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.set_time	= meson_rtc_settime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* NVMEM interface layer functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int meson_rtc_regmem_read(void *context, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 				 void *buf, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	struct meson_rtc *rtc = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	unsigned int read_offset, read_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	read_offset = RTC_REGMEM_0 + (offset / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	read_size = bytes / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	return regmap_bulk_read(rtc->serial, read_offset, buf, read_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int meson_rtc_regmem_write(void *context, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 				  void *buf, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	struct meson_rtc *rtc = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	unsigned int write_offset, write_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	write_offset = RTC_REGMEM_0 + (offset / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	write_size = bytes / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return regmap_bulk_write(rtc->serial, write_offset, buf, write_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int meson_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	struct nvmem_config meson_rtc_nvmem_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		.name = "meson-rtc-regmem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		.type = NVMEM_TYPE_BATTERY_BACKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		.word_size = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		.stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		.size = 4 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		.reg_read = meson_rtc_regmem_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		.reg_write = meson_rtc_regmem_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	struct meson_rtc *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	u32 tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	rtc = devm_kzalloc(dev, sizeof(struct meson_rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	if (!rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	rtc->rtc = devm_rtc_allocate_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	if (IS_ERR(rtc->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		return PTR_ERR(rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	platform_set_drvdata(pdev, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	rtc->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	rtc->rtc->ops = &meson_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	rtc->rtc->range_max = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	rtc->peripheral = devm_regmap_init_mmio(dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 					&meson_rtc_peripheral_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (IS_ERR(rtc->peripheral)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		dev_err(dev, "failed to create peripheral regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		return PTR_ERR(rtc->peripheral);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	rtc->reset = devm_reset_control_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	if (IS_ERR(rtc->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		dev_err(dev, "missing reset line\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		return PTR_ERR(rtc->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	rtc->vdd = devm_regulator_get(dev, "vdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if (IS_ERR(rtc->vdd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		dev_err(dev, "failed to get the vdd-supply\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		return PTR_ERR(rtc->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	ret = regulator_enable(rtc->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		dev_err(dev, "failed to enable vdd-supply\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	ret = meson_rtc_write_static(rtc, MESON_STATIC_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		dev_err(dev, "failed to set static values\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		goto out_disable_vdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	rtc->serial = devm_regmap_init(dev, &meson_rtc_serial_bus, rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 				       &meson_rtc_serial_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	if (IS_ERR(rtc->serial)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		dev_err(dev, "failed to create serial regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		ret = PTR_ERR(rtc->serial);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		goto out_disable_vdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	 * check if we can read RTC counter, if not then the RTC is probably
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	 * not functional. If it isn't probably best to not bind.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	ret = regmap_read(rtc->serial, RTC_COUNTER, &tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		dev_err(dev, "cannot read RTC counter, RTC not functional\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		goto out_disable_vdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	meson_rtc_nvmem_config.priv = rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	ret = rtc_nvmem_register(rtc->rtc, &meson_rtc_nvmem_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		goto out_disable_vdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	ret = rtc_register_device(rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		goto out_disable_vdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) out_disable_vdd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	regulator_disable(rtc->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const struct of_device_id meson_rtc_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	{ .compatible = "amlogic,meson6-rtc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	{ .compatible = "amlogic,meson8-rtc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	{ .compatible = "amlogic,meson8b-rtc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	{ .compatible = "amlogic,meson8m2-rtc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MODULE_DEVICE_TABLE(of, meson_rtc_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static struct platform_driver meson_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	.probe		= meson_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		.name		= "meson-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		.of_match_table	= of_match_ptr(meson_rtc_dt_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) module_platform_driver(meson_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MODULE_DESCRIPTION("Amlogic Meson RTC Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MODULE_AUTHOR("Ben Dooks <ben.doosk@codethink.co.uk>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MODULE_ALIAS("platform:meson-rtc");