^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SPI Driver for Microchip MCP795 RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) Josef Gajdusek <atx@atx.name>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * based on other Linux RTC drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Device datasheet:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * https://ww1.microchip.com/downloads/en/DeviceDoc/22280A.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/printk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* MCP795 Instructions, see datasheet table 3-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MCP795_EEREAD 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MCP795_EEWRITE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MCP795_EEWRDI 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MCP795_EEWREN 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MCP795_SRREAD 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MCP795_SRWRITE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MCP795_READ 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MCP795_WRITE 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MCP795_UNLOCK 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MCP795_IDWRITE 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MCP795_IDREAD 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MCP795_CLRWDT 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MCP795_CLRRAM 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* MCP795 RTCC registers, see datasheet table 4-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MCP795_REG_SECONDS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MCP795_REG_DAY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MCP795_REG_MONTH 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MCP795_REG_CONTROL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MCP795_REG_ALM0_SECONDS 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MCP795_REG_ALM0_DAY 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MCP795_ST_BIT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MCP795_24_BIT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MCP795_LP_BIT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MCP795_EXTOSC_BIT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MCP795_OSCON_BIT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MCP795_ALM0_BIT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MCP795_ALM1_BIT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MCP795_ALM0IF_BIT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MCP795_ALM0C0_BIT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MCP795_ALM0C1_BIT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MCP795_ALM0C2_BIT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SEC_PER_DAY (24 * 60 * 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int mcp795_rtcc_read(struct device *dev, u8 addr, u8 *buf, u8 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 tx[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) tx[0] = MCP795_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) tx[1] = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ret = spi_write_then_read(spi, tx, sizeof(tx), buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) dev_err(dev, "Failed reading %d bytes from address %x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) count, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int mcp795_rtcc_write(struct device *dev, u8 addr, u8 *data, u8 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u8 tx[257];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) tx[0] = MCP795_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) tx[1] = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) memcpy(&tx[2], data, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ret = spi_write(spi, tx, 2 + count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dev_err(dev, "Failed to write %d bytes to address %x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) count, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int mcp795_rtcc_set_bits(struct device *dev, u8 addr, u8 mask, u8 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ret = mcp795_rtcc_read(dev, addr, &tmp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if ((tmp & mask) != state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) tmp = (tmp & ~mask) | state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ret = mcp795_rtcc_write(dev, addr, &tmp, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int mcp795_stop_oscillator(struct device *dev, bool *extosc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int retries = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ret = mcp795_rtcc_set_bits(dev, MCP795_REG_SECONDS, MCP795_ST_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ret = mcp795_rtcc_read(dev, MCP795_REG_CONTROL, &data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *extosc = !!(data & MCP795_EXTOSC_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ret = mcp795_rtcc_set_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* wait for the OSCON bit to clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) usleep_range(700, 800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ret = mcp795_rtcc_read(dev, MCP795_REG_DAY, &data, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (!(data & MCP795_OSCON_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) } while (--retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return !retries ? -EIO : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int mcp795_start_oscillator(struct device *dev, bool *extosc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (extosc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 data = *extosc ? MCP795_EXTOSC_BIT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ret = mcp795_rtcc_set_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dev, MCP795_REG_CONTROL, MCP795_EXTOSC_BIT, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return mcp795_rtcc_set_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dev, MCP795_REG_SECONDS, MCP795_ST_BIT, MCP795_ST_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Enable or disable Alarm 0 in RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int mcp795_update_alarm(struct device *dev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dev_dbg(dev, "%s alarm\n", enable ? "Enable" : "Disable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* clear ALM0IF (Alarm 0 Interrupt Flag) bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ret = mcp795_rtcc_set_bits(dev, MCP795_REG_ALM0_DAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MCP795_ALM0IF_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* enable alarm 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MCP795_ALM0_BIT, MCP795_ALM0_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* disable alarm 0 and alarm 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = mcp795_rtcc_set_bits(dev, MCP795_REG_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MCP795_ALM0_BIT | MCP795_ALM1_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int mcp795_set_time(struct device *dev, struct rtc_time *tim)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u8 data[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) bool extosc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Stop RTC and store current value of EXTOSC bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ret = mcp795_stop_oscillator(dev, &extosc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Read first, so we can leave config bits untouched */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) data[0] = (data[0] & 0x80) | bin2bcd(tim->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) data[1] = (data[1] & 0x80) | bin2bcd(tim->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) data[2] = bin2bcd(tim->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) data[3] = (data[3] & 0xF8) | bin2bcd(tim->tm_wday + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) data[4] = bin2bcd(tim->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) data[5] = (data[5] & MCP795_LP_BIT) | bin2bcd(tim->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (tim->tm_year > 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) tim->tm_year -= 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) data[6] = bin2bcd(tim->tm_year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Always write the date and month using a separate Write command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * This is a workaround for a know silicon issue that some combinations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * of date and month values may result in the date being reset to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ret = mcp795_rtcc_write(dev, MCP795_REG_SECONDS, data, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = mcp795_rtcc_write(dev, MCP795_REG_MONTH, &data[5], 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Start back RTC and restore previous value of EXTOSC bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * There is no need to clear EXTOSC bit when the previous value was 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * because it was already cleared when stopping the RTC oscillator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ret = mcp795_start_oscillator(dev, extosc ? &extosc : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_dbg(dev, "Set mcp795: %ptR\n", tim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int mcp795_read_time(struct device *dev, struct rtc_time *tim)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u8 data[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ret = mcp795_rtcc_read(dev, MCP795_REG_SECONDS, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) tim->tm_sec = bcd2bin(data[0] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) tim->tm_min = bcd2bin(data[1] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) tim->tm_hour = bcd2bin(data[2] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) tim->tm_wday = bcd2bin(data[3] & 0x07) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) tim->tm_mday = bcd2bin(data[4] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) tim->tm_mon = bcd2bin(data[5] & 0x1F) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) tim->tm_year = bcd2bin(data[6]) + 100; /* Assume we are in 20xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dev_dbg(dev, "Read from mcp795: %ptR\n", tim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int mcp795_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct rtc_time now_tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) time64_t now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) time64_t later;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u8 tmp[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Read current time from RTC hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ret = mcp795_read_time(dev, &now_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Get the number of seconds since 1970 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) now = rtc_tm_to_time64(&now_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) later = rtc_tm_to_time64(&alm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (later <= now)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* make sure alarm fires within the next one year */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if ((later - now) >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) (SEC_PER_DAY * (365 + is_leap_year(alm->time.tm_year))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return -EDOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* disable alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ret = mcp795_update_alarm(dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Read registers, so we can leave configuration bits untouched */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ret = mcp795_rtcc_read(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) alm->time.tm_year = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) alm->time.tm_isdst = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) alm->time.tm_yday = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) tmp[0] = (tmp[0] & 0x80) | bin2bcd(alm->time.tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) tmp[1] = (tmp[1] & 0x80) | bin2bcd(alm->time.tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) tmp[2] = (tmp[2] & 0xE0) | bin2bcd(alm->time.tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) tmp[3] = (tmp[3] & 0x80) | bin2bcd(alm->time.tm_wday + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* set alarm match: seconds, minutes, hour, day, date and month */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) tmp[3] |= (MCP795_ALM0C2_BIT | MCP795_ALM0C1_BIT | MCP795_ALM0C0_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) tmp[4] = (tmp[4] & 0xC0) | bin2bcd(alm->time.tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) tmp[5] = (tmp[5] & 0xE0) | bin2bcd(alm->time.tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ret = mcp795_rtcc_write(dev, MCP795_REG_ALM0_SECONDS, tmp, sizeof(tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* enable alarm if requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (alm->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ret = mcp795_update_alarm(dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev_dbg(dev, "Alarm IRQ armed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev_dbg(dev, "Set alarm: %ptRdr(%d) %ptRt\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) &alm->time, alm->time.tm_wday, &alm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int mcp795_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u8 data[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ret = mcp795_rtcc_read(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dev, MCP795_REG_ALM0_SECONDS, data, sizeof(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) alm->time.tm_sec = bcd2bin(data[0] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) alm->time.tm_min = bcd2bin(data[1] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) alm->time.tm_hour = bcd2bin(data[2] & 0x1F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) alm->time.tm_wday = bcd2bin(data[3] & 0x07) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) alm->time.tm_mday = bcd2bin(data[4] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) alm->time.tm_mon = bcd2bin(data[5] & 0x1F) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) alm->time.tm_year = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) alm->time.tm_isdst = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) alm->time.tm_yday = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_dbg(dev, "Read alarm: %ptRdr(%d) %ptRt\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) &alm->time, alm->time.tm_wday, &alm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int mcp795_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return mcp795_update_alarm(dev, !!enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static irqreturn_t mcp795_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct spi_device *spi = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct rtc_device *rtc = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct mutex *lock = &rtc->ops_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) mutex_lock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Disable alarm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * There is no need to clear ALM0IF (Alarm 0 Interrupt Flag) bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * because it is done every time when alarm is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ret = mcp795_update_alarm(&spi->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) "Failed to disable alarm in IRQ (ret=%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) rtc_update_irq(rtc, 1, RTC_AF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) mutex_unlock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const struct rtc_class_ops mcp795_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .read_time = mcp795_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .set_time = mcp795_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .read_alarm = mcp795_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .set_alarm = mcp795_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .alarm_irq_enable = mcp795_alarm_irq_enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int mcp795_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) spi->mode = SPI_MODE_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) spi->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ret = spi_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_err(&spi->dev, "Unable to setup SPI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* Start the oscillator but don't set the value of EXTOSC bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) mcp795_start_oscillator(&spi->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Clear the 12 hour mode flag*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) mcp795_rtcc_set_bits(&spi->dev, 0x03, MCP795_24_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) rtc = devm_rtc_device_register(&spi->dev, "rtc-mcp795",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) &mcp795_rtc_ops, THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (IS_ERR(rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return PTR_ERR(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) spi_set_drvdata(spi, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (spi->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dev_dbg(&spi->dev, "Alarm support enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Clear any pending alarm (ALM0IF bit) before requesting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * the interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) mcp795_rtcc_set_bits(&spi->dev, MCP795_REG_ALM0_DAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MCP795_ALM0IF_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ret = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) mcp795_irq, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dev_name(&rtc->dev), spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dev_err(&spi->dev, "Failed to request IRQ: %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) spi->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) device_init_wakeup(&spi->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static const struct of_device_id mcp795_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) { .compatible = "maxim,mcp795" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) MODULE_DEVICE_TABLE(of, mcp795_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static struct spi_driver mcp795_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .name = "rtc-mcp795",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .of_match_table = of_match_ptr(mcp795_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .probe = mcp795_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) module_spi_driver(mcp795_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MODULE_DESCRIPTION("MCP795 RTC SPI Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MODULE_AUTHOR("Josef Gajdusek <atx@atx.name>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MODULE_ALIAS("spi:mcp795");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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