^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // RTC driver for Maxim MAX77686 and MAX77802
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2012 Samsung Electronics Co.Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // based on rtc-max8997.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/max77686-private.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MAX77686_I2C_ADDR_RTC (0x0C >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MAX77620_I2C_ADDR_RTC 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MAX77686_INVALID_I2C_ADDR (-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Define non existing register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MAX77686_INVALID_REG (-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* RTC Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BCD_EN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BCD_EN_MASK BIT(BCD_EN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MODEL24_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MODEL24_MASK BIT(MODEL24_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* RTC Update Register1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RTC_UDR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RTC_UDR_MASK BIT(RTC_UDR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RTC_RBUDR_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RTC_RBUDR_MASK BIT(RTC_RBUDR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* RTC Hour register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HOUR_PM_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HOUR_PM_MASK BIT(HOUR_PM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* RTC Alarm Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ALARM_ENABLE_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ALARM_ENABLE_MASK BIT(ALARM_ENABLE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define REG_RTC_NONE 0xdeadbeef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * MAX77802 has separate register (RTCAE1) for alarm enable instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * using 1 bit from registers RTC{SEC,MIN,HOUR,DAY,MONTH,YEAR,DATE}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * as in done in MAX77686.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MAX77802_ALARM_ENABLE_VALUE 0x77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) RTC_SEC = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) RTC_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) RTC_HOUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) RTC_WEEKDAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) RTC_MONTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) RTC_YEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) RTC_DATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) RTC_NR_TIME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct max77686_rtc_driver_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Minimum usecs needed for a RTC update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned long delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Mask used to read RTC registers value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Registers offset to I2C addresses map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) const unsigned int *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Has a separate alarm enable register? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) bool alarm_enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* I2C address for RTC block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int rtc_i2c_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* RTC interrupt via platform resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) bool rtc_irq_from_platform;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Pending alarm status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int alarm_pending_status_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* RTC IRQ CHIP for regmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) const struct regmap_irq_chip *rtc_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* regmap configuration for the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const struct regmap_config *regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct max77686_rtc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct i2c_client *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct rtc_device *rtc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct regmap *rtc_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const struct max77686_rtc_driver_data *drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct regmap_irq_chip_data *rtc_irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int rtc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int rtc_24hr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) enum MAX77686_RTC_OP {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MAX77686_RTC_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MAX77686_RTC_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* These are not registers but just offsets that are mapped to addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) enum max77686_rtc_reg_offset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) REG_RTC_CONTROLM = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) REG_RTC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) REG_RTC_UPDATE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) REG_WTSR_SMPL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) REG_RTC_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) REG_RTC_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) REG_RTC_HOUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) REG_RTC_WEEKDAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) REG_RTC_MONTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) REG_RTC_YEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) REG_RTC_DATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) REG_ALARM1_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) REG_ALARM1_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) REG_ALARM1_HOUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) REG_ALARM1_WEEKDAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) REG_ALARM1_MONTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) REG_ALARM1_YEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) REG_ALARM1_DATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) REG_ALARM2_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) REG_ALARM2_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) REG_ALARM2_HOUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) REG_ALARM2_WEEKDAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) REG_ALARM2_MONTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) REG_ALARM2_YEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) REG_ALARM2_DATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) REG_RTC_AE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) REG_RTC_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Maps RTC registers offset to the MAX77686 register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const unsigned int max77686_map[REG_RTC_END] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) [REG_RTC_CONTROLM] = MAX77686_RTC_CONTROLM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) [REG_RTC_CONTROL] = MAX77686_RTC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) [REG_RTC_UPDATE0] = MAX77686_RTC_UPDATE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) [REG_WTSR_SMPL_CNTL] = MAX77686_WTSR_SMPL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) [REG_RTC_SEC] = MAX77686_RTC_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) [REG_RTC_MIN] = MAX77686_RTC_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) [REG_RTC_HOUR] = MAX77686_RTC_HOUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) [REG_RTC_WEEKDAY] = MAX77686_RTC_WEEKDAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) [REG_RTC_MONTH] = MAX77686_RTC_MONTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) [REG_RTC_YEAR] = MAX77686_RTC_YEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) [REG_RTC_DATE] = MAX77686_RTC_DATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) [REG_ALARM1_SEC] = MAX77686_ALARM1_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) [REG_ALARM1_MIN] = MAX77686_ALARM1_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [REG_ALARM1_HOUR] = MAX77686_ALARM1_HOUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [REG_ALARM1_WEEKDAY] = MAX77686_ALARM1_WEEKDAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) [REG_ALARM1_MONTH] = MAX77686_ALARM1_MONTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [REG_ALARM1_YEAR] = MAX77686_ALARM1_YEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [REG_ALARM1_DATE] = MAX77686_ALARM1_DATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) [REG_ALARM2_SEC] = MAX77686_ALARM2_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) [REG_ALARM2_MIN] = MAX77686_ALARM2_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) [REG_ALARM2_HOUR] = MAX77686_ALARM2_HOUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [REG_ALARM2_WEEKDAY] = MAX77686_ALARM2_WEEKDAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) [REG_ALARM2_MONTH] = MAX77686_ALARM2_MONTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) [REG_ALARM2_YEAR] = MAX77686_ALARM2_YEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [REG_ALARM2_DATE] = MAX77686_ALARM2_DATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [REG_RTC_AE1] = REG_RTC_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct regmap_irq max77686_rtc_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* RTC interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) REGMAP_IRQ_REG(0, 0, MAX77686_RTCINT_RTC60S_MSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) REGMAP_IRQ_REG(1, 0, MAX77686_RTCINT_RTCA1_MSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) REGMAP_IRQ_REG(2, 0, MAX77686_RTCINT_RTCA2_MSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) REGMAP_IRQ_REG(3, 0, MAX77686_RTCINT_SMPL_MSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) REGMAP_IRQ_REG(4, 0, MAX77686_RTCINT_RTC1S_MSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) REGMAP_IRQ_REG(5, 0, MAX77686_RTCINT_WTSR_MSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const struct regmap_irq_chip max77686_rtc_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .name = "max77686-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .status_base = MAX77686_RTC_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .mask_base = MAX77686_RTC_INTM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .num_regs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .irqs = max77686_rtc_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .num_irqs = ARRAY_SIZE(max77686_rtc_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const struct regmap_config max77686_rtc_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const struct max77686_rtc_driver_data max77686_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .delay = 16000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .mask = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .map = max77686_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .alarm_enable_reg = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .rtc_irq_from_platform = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .alarm_pending_status_reg = MAX77686_REG_STATUS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .rtc_i2c_addr = MAX77686_I2C_ADDR_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .rtc_irq_chip = &max77686_rtc_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .regmap_config = &max77686_rtc_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const struct regmap_config max77620_rtc_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .use_single_write = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct max77686_rtc_driver_data max77620_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .delay = 16000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .mask = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .map = max77686_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .alarm_enable_reg = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .rtc_irq_from_platform = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .alarm_pending_status_reg = MAX77686_INVALID_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .rtc_i2c_addr = MAX77620_I2C_ADDR_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .rtc_irq_chip = &max77686_rtc_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .regmap_config = &max77620_rtc_regmap_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const unsigned int max77802_map[REG_RTC_END] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) [REG_RTC_CONTROLM] = MAX77802_RTC_CONTROLM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) [REG_RTC_CONTROL] = MAX77802_RTC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) [REG_RTC_UPDATE0] = MAX77802_RTC_UPDATE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) [REG_WTSR_SMPL_CNTL] = MAX77802_WTSR_SMPL_CNTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) [REG_RTC_SEC] = MAX77802_RTC_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) [REG_RTC_MIN] = MAX77802_RTC_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) [REG_RTC_HOUR] = MAX77802_RTC_HOUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) [REG_RTC_WEEKDAY] = MAX77802_RTC_WEEKDAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) [REG_RTC_MONTH] = MAX77802_RTC_MONTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) [REG_RTC_YEAR] = MAX77802_RTC_YEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) [REG_RTC_DATE] = MAX77802_RTC_DATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) [REG_ALARM1_SEC] = MAX77802_ALARM1_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) [REG_ALARM1_MIN] = MAX77802_ALARM1_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) [REG_ALARM1_HOUR] = MAX77802_ALARM1_HOUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) [REG_ALARM1_WEEKDAY] = MAX77802_ALARM1_WEEKDAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) [REG_ALARM1_MONTH] = MAX77802_ALARM1_MONTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) [REG_ALARM1_YEAR] = MAX77802_ALARM1_YEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) [REG_ALARM1_DATE] = MAX77802_ALARM1_DATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) [REG_ALARM2_SEC] = MAX77802_ALARM2_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) [REG_ALARM2_MIN] = MAX77802_ALARM2_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) [REG_ALARM2_HOUR] = MAX77802_ALARM2_HOUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) [REG_ALARM2_WEEKDAY] = MAX77802_ALARM2_WEEKDAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) [REG_ALARM2_MONTH] = MAX77802_ALARM2_MONTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) [REG_ALARM2_YEAR] = MAX77802_ALARM2_YEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) [REG_ALARM2_DATE] = MAX77802_ALARM2_DATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) [REG_RTC_AE1] = MAX77802_RTC_AE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const struct regmap_irq_chip max77802_rtc_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .name = "max77802-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .status_base = MAX77802_RTC_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .mask_base = MAX77802_RTC_INTM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .num_regs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .irqs = max77686_rtc_irqs, /* same masks as 77686 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .num_irqs = ARRAY_SIZE(max77686_rtc_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const struct max77686_rtc_driver_data max77802_drv_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .delay = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .map = max77802_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .alarm_enable_reg = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .rtc_irq_from_platform = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .alarm_pending_status_reg = MAX77686_REG_STATUS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .rtc_i2c_addr = MAX77686_INVALID_I2C_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .rtc_irq_chip = &max77802_rtc_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static void max77686_rtc_data_to_tm(u8 *data, struct rtc_time *tm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct max77686_rtc_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u8 mask = info->drv_data->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) tm->tm_sec = data[RTC_SEC] & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) tm->tm_min = data[RTC_MIN] & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (info->rtc_24hr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) tm->tm_hour = data[RTC_HOUR] & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) tm->tm_hour = data[RTC_HOUR] & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (data[RTC_HOUR] & HOUR_PM_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) tm->tm_hour += 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* Only a single bit is set in data[], so fls() would be equivalent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) tm->tm_wday = ffs(data[RTC_WEEKDAY] & mask) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) tm->tm_mday = data[RTC_DATE] & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) tm->tm_mon = (data[RTC_MONTH] & 0x0f) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) tm->tm_year = data[RTC_YEAR] & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) tm->tm_yday = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) tm->tm_isdst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * MAX77686 uses 1 bit from sec/min/hour/etc RTC registers and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * year values are just 0..99 so add 100 to support up to 2099.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (!info->drv_data->alarm_enable_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) tm->tm_year += 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int max77686_rtc_tm_to_data(struct rtc_time *tm, u8 *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct max77686_rtc_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) data[RTC_SEC] = tm->tm_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) data[RTC_MIN] = tm->tm_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) data[RTC_HOUR] = tm->tm_hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) data[RTC_WEEKDAY] = 1 << tm->tm_wday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) data[RTC_DATE] = tm->tm_mday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) data[RTC_MONTH] = tm->tm_mon + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (info->drv_data->alarm_enable_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) data[RTC_YEAR] = tm->tm_year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) data[RTC_YEAR] = tm->tm_year > 100 ? (tm->tm_year - 100) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (tm->tm_year < 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_err(info->dev, "RTC cannot handle the year %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 1900 + tm->tm_year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int max77686_rtc_update(struct max77686_rtc_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) enum MAX77686_RTC_OP op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned long delay = info->drv_data->delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (op == MAX77686_RTC_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) data = 1 << RTC_UDR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) data = 1 << RTC_RBUDR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ret = regmap_update_bits(info->rtc_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) info->drv_data->map[REG_RTC_UPDATE0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) data, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) dev_err(info->dev, "Fail to write update reg(ret=%d, data=0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ret, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Minimum delay required before RTC update. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) usleep_range(delay, delay * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int max77686_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct max77686_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u8 data[RTC_NR_TIME];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) mutex_lock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ret = max77686_rtc_update(info, MAX77686_RTC_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ret = regmap_bulk_read(info->rtc_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) info->drv_data->map[REG_RTC_SEC],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) data, ARRAY_SIZE(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dev_err(info->dev, "Fail to read time reg(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) max77686_rtc_data_to_tm(data, tm, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int max77686_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct max77686_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u8 data[RTC_NR_TIME];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ret = max77686_rtc_tm_to_data(tm, data, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) mutex_lock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ret = regmap_bulk_write(info->rtc_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) info->drv_data->map[REG_RTC_SEC],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) data, ARRAY_SIZE(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_err(info->dev, "Fail to write time reg(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int max77686_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct max77686_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u8 data[RTC_NR_TIME];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) const unsigned int *map = info->drv_data->map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) mutex_lock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ret = max77686_rtc_update(info, MAX77686_RTC_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) data, ARRAY_SIZE(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) max77686_rtc_data_to_tm(data, &alrm->time, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) alrm->enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (info->drv_data->alarm_enable_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (map[REG_RTC_AE1] == REG_RTC_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev_err(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) "alarm enable register not set(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ret = regmap_read(info->rtc_regmap, map[REG_RTC_AE1], &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dev_err(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) "fail to read alarm enable(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) alrm->enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) for (i = 0; i < ARRAY_SIZE(data); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (data[i] & ALARM_ENABLE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) alrm->enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) alrm->pending = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (info->drv_data->alarm_pending_status_reg == MAX77686_INVALID_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = regmap_read(info->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) info->drv_data->alarm_pending_status_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dev_err(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) "Fail to read alarm pending status reg(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (val & (1 << 4)) /* RTCA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) alrm->pending = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int max77686_rtc_stop_alarm(struct max77686_rtc_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u8 data[RTC_NR_TIME];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct rtc_time tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) const unsigned int *map = info->drv_data->map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (!mutex_is_locked(&info->lock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ret = max77686_rtc_update(info, MAX77686_RTC_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (info->drv_data->alarm_enable_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (map[REG_RTC_AE1] == REG_RTC_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dev_err(info->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) "alarm enable register not set(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ret = regmap_write(info->rtc_regmap, map[REG_RTC_AE1], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) data, ARRAY_SIZE(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) max77686_rtc_data_to_tm(data, &tm, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) for (i = 0; i < ARRAY_SIZE(data); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) data[i] &= ~ALARM_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ret = regmap_bulk_write(info->rtc_regmap, map[REG_ALARM1_SEC],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) data, ARRAY_SIZE(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int max77686_rtc_start_alarm(struct max77686_rtc_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u8 data[RTC_NR_TIME];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct rtc_time tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) const unsigned int *map = info->drv_data->map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (!mutex_is_locked(&info->lock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) dev_warn(info->dev, "%s: should have mutex locked\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ret = max77686_rtc_update(info, MAX77686_RTC_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (info->drv_data->alarm_enable_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ret = regmap_write(info->rtc_regmap, map[REG_RTC_AE1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) MAX77802_ALARM_ENABLE_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ret = regmap_bulk_read(info->rtc_regmap, map[REG_ALARM1_SEC],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) data, ARRAY_SIZE(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev_err(info->dev, "Fail to read alarm reg(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) max77686_rtc_data_to_tm(data, &tm, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) data[RTC_SEC] |= (1 << ALARM_ENABLE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) data[RTC_MIN] |= (1 << ALARM_ENABLE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) data[RTC_HOUR] |= (1 << ALARM_ENABLE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) data[RTC_WEEKDAY] &= ~ALARM_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (data[RTC_MONTH] & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) data[RTC_MONTH] |= (1 << ALARM_ENABLE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (data[RTC_YEAR] & info->drv_data->mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) data[RTC_YEAR] |= (1 << ALARM_ENABLE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (data[RTC_DATE] & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) data[RTC_DATE] |= (1 << ALARM_ENABLE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ret = regmap_bulk_write(info->rtc_regmap, map[REG_ALARM1_SEC],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) data, ARRAY_SIZE(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static int max77686_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct max77686_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u8 data[RTC_NR_TIME];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ret = max77686_rtc_tm_to_data(&alrm->time, data, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) mutex_lock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ret = max77686_rtc_stop_alarm(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ret = regmap_bulk_write(info->rtc_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) info->drv_data->map[REG_ALARM1_SEC],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) data, ARRAY_SIZE(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) dev_err(info->dev, "Fail to write alarm reg(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (alrm->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ret = max77686_rtc_start_alarm(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int max77686_rtc_alarm_irq_enable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct max77686_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) mutex_lock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ret = max77686_rtc_start_alarm(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ret = max77686_rtc_stop_alarm(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) mutex_unlock(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static irqreturn_t max77686_rtc_alarm_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct max77686_rtc_info *info = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) dev_dbg(info->dev, "RTC alarm IRQ: %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static const struct rtc_class_ops max77686_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .read_time = max77686_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .set_time = max77686_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .read_alarm = max77686_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .set_alarm = max77686_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .alarm_irq_enable = max77686_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static int max77686_rtc_init_reg(struct max77686_rtc_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) u8 data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* Set RTC control register : Binary mode, 24hour mdoe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) data[0] = (1 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) data[1] = (0 << BCD_EN_SHIFT) | (1 << MODEL24_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) info->rtc_24hr_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) ret = regmap_bulk_write(info->rtc_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) info->drv_data->map[REG_RTC_CONTROLM],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) data, ARRAY_SIZE(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dev_err(info->dev, "Fail to write controlm reg(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ret = max77686_rtc_update(info, MAX77686_RTC_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static int max77686_init_rtc_regmap(struct max77686_rtc_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct device *parent = info->dev->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct i2c_client *parent_i2c = to_i2c_client(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (info->drv_data->rtc_irq_from_platform) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct platform_device *pdev = to_platform_device(info->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) info->rtc_irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (info->rtc_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return info->rtc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) info->rtc_irq = parent_i2c->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) info->regmap = dev_get_regmap(parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (!info->regmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dev_err(info->dev, "Failed to get rtc regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (info->drv_data->rtc_i2c_addr == MAX77686_INVALID_I2C_ADDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) info->rtc_regmap = info->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) goto add_rtc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) info->rtc = devm_i2c_new_dummy_device(info->dev, parent_i2c->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) info->drv_data->rtc_i2c_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (IS_ERR(info->rtc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) dev_err(info->dev, "Failed to allocate I2C device for RTC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return PTR_ERR(info->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) info->rtc_regmap = devm_regmap_init_i2c(info->rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) info->drv_data->regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (IS_ERR(info->rtc_regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ret = PTR_ERR(info->rtc_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) dev_err(info->dev, "Failed to allocate RTC regmap: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) add_rtc_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ret = regmap_add_irq_chip(info->rtc_regmap, info->rtc_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) IRQF_ONESHOT | IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 0, info->drv_data->rtc_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) &info->rtc_irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) dev_err(info->dev, "Failed to add RTC irq chip: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static int max77686_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct max77686_rtc_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) const struct platform_device_id *id = platform_get_device_id(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) info = devm_kzalloc(&pdev->dev, sizeof(struct max77686_rtc_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) mutex_init(&info->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) info->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) info->drv_data = (const struct max77686_rtc_driver_data *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ret = max77686_init_rtc_regmap(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) platform_set_drvdata(pdev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) ret = max77686_rtc_init_reg(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) dev_err(&pdev->dev, "Failed to initialize RTC reg:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) goto err_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) info->rtc_dev = devm_rtc_device_register(&pdev->dev, id->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) &max77686_rtc_ops, THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (IS_ERR(info->rtc_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ret = PTR_ERR(info->rtc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dev_err(&pdev->dev, "Failed to register RTC device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) goto err_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) info->virq = regmap_irq_get_virq(info->rtc_irq_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) MAX77686_RTCIRQ_RTCA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (info->virq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) goto err_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ret = request_threaded_irq(info->virq, NULL, max77686_rtc_alarm_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) "rtc-alarm1", info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) info->virq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) goto err_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) err_rtc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) regmap_del_irq_chip(info->rtc_irq, info->rtc_irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static int max77686_rtc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct max77686_rtc_info *info = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) free_irq(info->virq, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) regmap_del_irq_chip(info->rtc_irq, info->rtc_irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static int max77686_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct max77686_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (device_may_wakeup(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct max77686_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ret = enable_irq_wake(info->virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * If the main IRQ (not virtual) is the parent IRQ, then it must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * disabled during suspend because if it happens while suspended it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * will be handled before resuming I2C.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) * Since Main IRQ is shared, all its users should disable it to be sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * it won't fire while one of them is still suspended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (!info->drv_data->rtc_irq_from_platform)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) disable_irq(info->rtc_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static int max77686_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct max77686_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (!info->drv_data->rtc_irq_from_platform)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) enable_irq(info->rtc_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (device_may_wakeup(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct max77686_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return disable_irq_wake(info->virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static SIMPLE_DEV_PM_OPS(max77686_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) max77686_rtc_suspend, max77686_rtc_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static const struct platform_device_id rtc_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) { "max77686-rtc", .driver_data = (kernel_ulong_t)&max77686_drv_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) { "max77802-rtc", .driver_data = (kernel_ulong_t)&max77802_drv_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) { "max77620-rtc", .driver_data = (kernel_ulong_t)&max77620_drv_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) MODULE_DEVICE_TABLE(platform, rtc_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static struct platform_driver max77686_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .name = "max77686-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .pm = &max77686_rtc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .probe = max77686_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .remove = max77686_rtc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .id_table = rtc_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) module_platform_driver(max77686_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) MODULE_DESCRIPTION("Maxim MAX77686 RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) MODULE_AUTHOR("Chiwoong Byun <woong.byun@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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