^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ST M48T86 / Dallas DS12887 RTC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2006 Tower Technologies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Alessandro Zummo <a.zummo@towertech.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This drivers only supports the clock running in BCD and 24H mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * If it will be ever adapted to binary and 12H mode, care must be taken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * to not introduce bugs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define M48T86_SEC 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define M48T86_SECALRM 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define M48T86_MIN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define M48T86_MINALRM 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define M48T86_HOUR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define M48T86_HOURALRM 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define M48T86_DOW 0x06 /* 1 = sunday */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define M48T86_DOM 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define M48T86_MONTH 0x08 /* 1 - 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define M48T86_YEAR 0x09 /* 0 - 99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define M48T86_A 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define M48T86_B 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define M48T86_B_SET BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define M48T86_B_DM BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define M48T86_B_H24 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define M48T86_C 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define M48T86_D 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define M48T86_D_VRT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define M48T86_NVRAM(x) (0x0e + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define M48T86_NVRAM_LEN 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct m48t86_rtc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void __iomem *index_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void __iomem *data_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static unsigned char m48t86_readb(struct device *dev, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct m48t86_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned char value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) writeb(addr, info->index_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) value = readb(info->data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static void m48t86_writeb(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned char value, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct m48t86_rtc_info *info = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) writeb(addr, info->index_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) writeb(value, info->data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int m48t86_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned char reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) reg = m48t86_readb(dev, M48T86_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (reg & M48T86_B_DM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* data (binary) mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) tm->tm_sec = m48t86_readb(dev, M48T86_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) tm->tm_min = m48t86_readb(dev, M48T86_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) tm->tm_hour = m48t86_readb(dev, M48T86_HOUR) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) tm->tm_mday = m48t86_readb(dev, M48T86_DOM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* tm_mon is 0-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) tm->tm_mon = m48t86_readb(dev, M48T86_MONTH) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) tm->tm_year = m48t86_readb(dev, M48T86_YEAR) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) tm->tm_wday = m48t86_readb(dev, M48T86_DOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* bcd mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) tm->tm_sec = bcd2bin(m48t86_readb(dev, M48T86_SEC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) tm->tm_min = bcd2bin(m48t86_readb(dev, M48T86_MIN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) tm->tm_hour = bcd2bin(m48t86_readb(dev, M48T86_HOUR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) tm->tm_mday = bcd2bin(m48t86_readb(dev, M48T86_DOM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* tm_mon is 0-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) tm->tm_mon = bcd2bin(m48t86_readb(dev, M48T86_MONTH)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) tm->tm_year = bcd2bin(m48t86_readb(dev, M48T86_YEAR)) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) tm->tm_wday = bcd2bin(m48t86_readb(dev, M48T86_DOW));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* correct the hour if the clock is in 12h mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (!(reg & M48T86_B_H24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (m48t86_readb(dev, M48T86_HOUR) & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) tm->tm_hour += 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int m48t86_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned char reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) reg = m48t86_readb(dev, M48T86_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* update flag and 24h mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) reg |= M48T86_B_SET | M48T86_B_H24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) m48t86_writeb(dev, reg, M48T86_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (reg & M48T86_B_DM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* data (binary) mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) m48t86_writeb(dev, tm->tm_sec, M48T86_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) m48t86_writeb(dev, tm->tm_min, M48T86_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) m48t86_writeb(dev, tm->tm_hour, M48T86_HOUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) m48t86_writeb(dev, tm->tm_mday, M48T86_DOM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) m48t86_writeb(dev, tm->tm_mon + 1, M48T86_MONTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) m48t86_writeb(dev, tm->tm_year % 100, M48T86_YEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) m48t86_writeb(dev, tm->tm_wday, M48T86_DOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* bcd mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) m48t86_writeb(dev, bin2bcd(tm->tm_sec), M48T86_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) m48t86_writeb(dev, bin2bcd(tm->tm_min), M48T86_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) m48t86_writeb(dev, bin2bcd(tm->tm_hour), M48T86_HOUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) m48t86_writeb(dev, bin2bcd(tm->tm_mday), M48T86_DOM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) m48t86_writeb(dev, bin2bcd(tm->tm_mon + 1), M48T86_MONTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) m48t86_writeb(dev, bin2bcd(tm->tm_year % 100), M48T86_YEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) m48t86_writeb(dev, bin2bcd(tm->tm_wday), M48T86_DOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* update ended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) reg &= ~M48T86_B_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) m48t86_writeb(dev, reg, M48T86_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int m48t86_rtc_proc(struct device *dev, struct seq_file *seq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned char reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) reg = m48t86_readb(dev, M48T86_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) seq_printf(seq, "mode\t\t: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) (reg & M48T86_B_DM) ? "binary" : "bcd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) reg = m48t86_readb(dev, M48T86_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) seq_printf(seq, "battery\t\t: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) (reg & M48T86_D_VRT) ? "ok" : "exhausted");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct rtc_class_ops m48t86_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .read_time = m48t86_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .set_time = m48t86_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .proc = m48t86_rtc_proc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int m48t86_nvram_read(void *priv, unsigned int off, void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct device *dev = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) for (i = 0; i < count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ((u8 *)buf)[i] = m48t86_readb(dev, M48T86_NVRAM(off + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int m48t86_nvram_write(void *priv, unsigned int off, void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct device *dev = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) for (i = 0; i < count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) m48t86_writeb(dev, ((u8 *)buf)[i], M48T86_NVRAM(off + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * The RTC is an optional feature at purchase time on some Technologic Systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * boards. Verify that it actually exists by checking if the last two bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * of the NVRAM can be changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * This is based on the method used in their rtc7800.c example.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static bool m48t86_verify_chip(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned int offset0 = M48T86_NVRAM(M48T86_NVRAM_LEN - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int offset1 = M48T86_NVRAM(M48T86_NVRAM_LEN - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned char tmp0, tmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) tmp0 = m48t86_readb(&pdev->dev, offset0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) tmp1 = m48t86_readb(&pdev->dev, offset1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) m48t86_writeb(&pdev->dev, 0x00, offset0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) m48t86_writeb(&pdev->dev, 0x55, offset1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (m48t86_readb(&pdev->dev, offset1) == 0x55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) m48t86_writeb(&pdev->dev, 0xaa, offset1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (m48t86_readb(&pdev->dev, offset1) == 0xaa &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) m48t86_readb(&pdev->dev, offset0) == 0x00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) m48t86_writeb(&pdev->dev, tmp0, offset0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) m48t86_writeb(&pdev->dev, tmp1, offset1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int m48t86_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct m48t86_rtc_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned char reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct nvmem_config m48t86_nvmem_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .name = "m48t86_nvram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .word_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .size = M48T86_NVRAM_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .reg_read = m48t86_nvram_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .reg_write = m48t86_nvram_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .priv = &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) info->index_reg = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (IS_ERR(info->index_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return PTR_ERR(info->index_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) info->data_reg = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (IS_ERR(info->data_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return PTR_ERR(info->data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_set_drvdata(&pdev->dev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (!m48t86_verify_chip(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dev_info(&pdev->dev, "RTC not present\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) info->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (IS_ERR(info->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return PTR_ERR(info->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) info->rtc->ops = &m48t86_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) info->rtc->nvram_old_abi = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) err = rtc_register_device(info->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) rtc_nvmem_register(info->rtc, &m48t86_nvmem_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* read battery status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) reg = m48t86_readb(&pdev->dev, M48T86_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_info(&pdev->dev, "battery %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) (reg & M48T86_D_VRT) ? "ok" : "exhausted");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static struct platform_driver m48t86_rtc_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .name = "rtc-m48t86",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .probe = m48t86_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) module_platform_driver(m48t86_rtc_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MODULE_AUTHOR("Alessandro Zummo <a.zummo@towertech.it>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MODULE_DESCRIPTION("M48T86 RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) MODULE_ALIAS("platform:rtc-m48t86");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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