^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ST M48T59 RTC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2007 Wind River Systems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Mark Zhan <rongkai.zhan@windriver.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/rtc/m48t59.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifndef NO_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define NO_IRQ (-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define M48T59_READ(reg) (pdata->read_byte(dev, pdata->offset + reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define M48T59_WRITE(val, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) (pdata->write_byte(dev, pdata->offset + reg, val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define M48T59_SET_BITS(mask, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) M48T59_WRITE((M48T59_READ(reg) | (mask)), (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define M48T59_CLEAR_BITS(mask, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) M48T59_WRITE((M48T59_READ(reg) & ~(mask)), (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct m48t59_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) spinlock_t lock; /* serialize the NVRAM and RTC access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * This is the generic access method when the chip is memory-mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) m48t59_mem_writeb(struct device *dev, u32 ofs, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct m48t59_private *m48t59 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) writeb(val, m48t59->ioaddr+ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) m48t59_mem_readb(struct device *dev, u32 ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct m48t59_private *m48t59 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return readb(m48t59->ioaddr+ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * NOTE: M48T59 only uses BCD mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int m48t59_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct m48t59_plat_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct m48t59_private *m48t59 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) spin_lock_irqsave(&m48t59->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Issue the READ command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) M48T59_SET_BITS(M48T59_CNTL_READ, M48T59_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) tm->tm_year = bcd2bin(M48T59_READ(M48T59_YEAR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* tm_mon is 0-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) tm->tm_mon = bcd2bin(M48T59_READ(M48T59_MONTH)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) tm->tm_mday = bcd2bin(M48T59_READ(M48T59_MDAY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) val = M48T59_READ(M48T59_WDAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if ((pdata->type == M48T59RTC_TYPE_M48T59) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) (val & M48T59_WDAY_CEB) && (val & M48T59_WDAY_CB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) dev_dbg(dev, "Century bit is enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) tm->tm_year += 100; /* one century */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #ifdef CONFIG_SPARC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Sun SPARC machines count years since 1968 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) tm->tm_year += 68;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) tm->tm_wday = bcd2bin(val & 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) tm->tm_hour = bcd2bin(M48T59_READ(M48T59_HOUR) & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) tm->tm_min = bcd2bin(M48T59_READ(M48T59_MIN) & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) tm->tm_sec = bcd2bin(M48T59_READ(M48T59_SEC) & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Clear the READ bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) M48T59_CLEAR_BITS(M48T59_CNTL_READ, M48T59_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) spin_unlock_irqrestore(&m48t59->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dev_dbg(dev, "RTC read time %ptR\n", tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int m48t59_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct m48t59_plat_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct m48t59_private *m48t59 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int year = tm->tm_year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #ifdef CONFIG_SPARC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Sun SPARC machines count years since 1968 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) year -= 68;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dev_dbg(dev, "RTC set time %04d-%02d-%02d %02d/%02d/%02d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) year + 1900, tm->tm_mon, tm->tm_mday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) tm->tm_hour, tm->tm_min, tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (year < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) spin_lock_irqsave(&m48t59->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Issue the WRITE command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) M48T59_SET_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) M48T59_WRITE((bin2bcd(tm->tm_sec) & 0x7F), M48T59_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) M48T59_WRITE((bin2bcd(tm->tm_min) & 0x7F), M48T59_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) M48T59_WRITE((bin2bcd(tm->tm_hour) & 0x3F), M48T59_HOUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) M48T59_WRITE((bin2bcd(tm->tm_mday) & 0x3F), M48T59_MDAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* tm_mon is 0-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) M48T59_WRITE((bin2bcd(tm->tm_mon + 1) & 0x1F), M48T59_MONTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) M48T59_WRITE(bin2bcd(year % 100), M48T59_YEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (pdata->type == M48T59RTC_TYPE_M48T59 && (year / 100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) val = (M48T59_WDAY_CEB | M48T59_WDAY_CB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) val |= (bin2bcd(tm->tm_wday) & 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) M48T59_WRITE(val, M48T59_WDAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Clear the WRITE bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) M48T59_CLEAR_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) spin_unlock_irqrestore(&m48t59->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * Read alarm time and date in RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int m48t59_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct m48t59_plat_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct m48t59_private *m48t59 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct rtc_time *tm = &alrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* If no irq, we don't support ALARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (m48t59->irq == NO_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) spin_lock_irqsave(&m48t59->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Issue the READ command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) M48T59_SET_BITS(M48T59_CNTL_READ, M48T59_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) tm->tm_year = bcd2bin(M48T59_READ(M48T59_YEAR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #ifdef CONFIG_SPARC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Sun SPARC machines count years since 1968 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) tm->tm_year += 68;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* tm_mon is 0-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) tm->tm_mon = bcd2bin(M48T59_READ(M48T59_MONTH)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) val = M48T59_READ(M48T59_WDAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if ((val & M48T59_WDAY_CEB) && (val & M48T59_WDAY_CB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) tm->tm_year += 100; /* one century */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) tm->tm_mday = bcd2bin(M48T59_READ(M48T59_ALARM_DATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) tm->tm_hour = bcd2bin(M48T59_READ(M48T59_ALARM_HOUR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) tm->tm_min = bcd2bin(M48T59_READ(M48T59_ALARM_MIN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) tm->tm_sec = bcd2bin(M48T59_READ(M48T59_ALARM_SEC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Clear the READ bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) M48T59_CLEAR_BITS(M48T59_CNTL_READ, M48T59_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) spin_unlock_irqrestore(&m48t59->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) dev_dbg(dev, "RTC read alarm time %ptR\n", tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return rtc_valid_tm(tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * Set alarm time and date in RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int m48t59_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct m48t59_plat_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct m48t59_private *m48t59 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct rtc_time *tm = &alrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u8 mday, hour, min, sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int year = tm->tm_year;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #ifdef CONFIG_SPARC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Sun SPARC machines count years since 1968 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) year -= 68;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* If no irq, we don't support ALARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (m48t59->irq == NO_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (year < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * 0xff means "always match"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) mday = tm->tm_mday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mday = (mday >= 1 && mday <= 31) ? bin2bcd(mday) : 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (mday == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) mday = M48T59_READ(M48T59_MDAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) hour = tm->tm_hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) hour = (hour < 24) ? bin2bcd(hour) : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) min = tm->tm_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) min = (min < 60) ? bin2bcd(min) : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) sec = tm->tm_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) sec = (sec < 60) ? bin2bcd(sec) : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) spin_lock_irqsave(&m48t59->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Issue the WRITE command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) M48T59_SET_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) M48T59_WRITE(mday, M48T59_ALARM_DATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) M48T59_WRITE(hour, M48T59_ALARM_HOUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) M48T59_WRITE(min, M48T59_ALARM_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) M48T59_WRITE(sec, M48T59_ALARM_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Clear the WRITE bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) M48T59_CLEAR_BITS(M48T59_CNTL_WRITE, M48T59_CNTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) spin_unlock_irqrestore(&m48t59->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev_dbg(dev, "RTC set alarm time %04d-%02d-%02d %02d/%02d/%02d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) year + 1900, tm->tm_mon, tm->tm_mday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) tm->tm_hour, tm->tm_min, tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * Handle commands from user-space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int m48t59_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct m48t59_plat_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct m48t59_private *m48t59 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) spin_lock_irqsave(&m48t59->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) M48T59_WRITE(M48T59_INTR_AFE, M48T59_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) M48T59_WRITE(0x00, M48T59_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) spin_unlock_irqrestore(&m48t59->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int m48t59_rtc_proc(struct device *dev, struct seq_file *seq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct m48t59_plat_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct m48t59_private *m48t59 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) spin_lock_irqsave(&m48t59->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) val = M48T59_READ(M48T59_FLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) spin_unlock_irqrestore(&m48t59->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) seq_printf(seq, "battery\t\t: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) (val & M48T59_FLAGS_BF) ? "low" : "normal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * IRQ handler for the RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static irqreturn_t m48t59_rtc_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct device *dev = (struct device *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct m48t59_plat_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct m48t59_private *m48t59 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u8 event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) spin_lock(&m48t59->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) event = M48T59_READ(M48T59_FLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) spin_unlock(&m48t59->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (event & M48T59_FLAGS_AF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) rtc_update_irq(m48t59->rtc, 1, (RTC_AF | RTC_IRQF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const struct rtc_class_ops m48t59_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .read_time = m48t59_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .set_time = m48t59_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .read_alarm = m48t59_rtc_readalarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .set_alarm = m48t59_rtc_setalarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .proc = m48t59_rtc_proc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .alarm_irq_enable = m48t59_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const struct rtc_class_ops m48t02_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .read_time = m48t59_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .set_time = m48t59_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int m48t59_nvram_read(void *priv, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct platform_device *pdev = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ssize_t cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u8 *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) spin_lock_irqsave(&m48t59->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) for (; cnt < size; cnt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) *buf++ = M48T59_READ(cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) spin_unlock_irqrestore(&m48t59->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static int m48t59_nvram_write(void *priv, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct platform_device *pdev = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct m48t59_private *m48t59 = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ssize_t cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u8 *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) spin_lock_irqsave(&m48t59->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) for (; cnt < size; cnt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) M48T59_WRITE(*buf++, cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) spin_unlock_irqrestore(&m48t59->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int m48t59_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct m48t59_plat_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct m48t59_private *m48t59 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) const struct rtc_class_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct nvmem_config nvmem_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .name = "m48t59-",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .word_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .reg_read = m48t59_nvram_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .reg_write = m48t59_nvram_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .priv = pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* This chip could be memory-mapped or I/O-mapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) res = platform_get_resource(pdev, IORESOURCE_IO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (res->flags & IORESOURCE_IO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* If we are I/O-mapped, the platform should provide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * the operations accessing chip registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!pdata || !pdata->write_byte || !pdata->read_byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) } else if (res->flags & IORESOURCE_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* we are memory-mapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Ensure we only kmalloc platform data once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) pdev->dev.platform_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (!pdata->type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) pdata->type = M48T59RTC_TYPE_M48T59;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Try to use the generic memory read/write ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (!pdata->write_byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) pdata->write_byte = m48t59_mem_writeb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (!pdata->read_byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) pdata->read_byte = m48t59_mem_readb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) m48t59 = devm_kzalloc(&pdev->dev, sizeof(*m48t59), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (!m48t59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) m48t59->ioaddr = pdata->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (!m48t59->ioaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* ioaddr not mapped externally */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) m48t59->ioaddr = devm_ioremap(&pdev->dev, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (!m48t59->ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* Try to get irq number. We also can work in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * the mode without IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) m48t59->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (m48t59->irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) m48t59->irq = NO_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (m48t59->irq != NO_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ret = devm_request_irq(&pdev->dev, m48t59->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) m48t59_rtc_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) "rtc-m48t59", &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) switch (pdata->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case M48T59RTC_TYPE_M48T59:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ops = &m48t59_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) pdata->offset = 0x1ff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) case M48T59RTC_TYPE_M48T02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ops = &m48t02_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) pdata->offset = 0x7f0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case M48T59RTC_TYPE_M48T08:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ops = &m48t02_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pdata->offset = 0x1ff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dev_err(&pdev->dev, "Unknown RTC type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) spin_lock_init(&m48t59->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) platform_set_drvdata(pdev, m48t59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) m48t59->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (IS_ERR(m48t59->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return PTR_ERR(m48t59->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) m48t59->rtc->nvram_old_abi = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) m48t59->rtc->ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) nvmem_cfg.size = pdata->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = rtc_nvmem_register(m48t59->rtc, &nvmem_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ret = rtc_register_device(m48t59->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* work with hotplug and coldplug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MODULE_ALIAS("platform:rtc-m48t59");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static struct platform_driver m48t59_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .name = "rtc-m48t59",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .probe = m48t59_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) module_platform_driver(m48t59_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) MODULE_AUTHOR("Mark Zhan <rongkai.zhan@windriver.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) MODULE_DESCRIPTION("M48T59/M48T02/M48T08 RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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