^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for ST M41T94 SPI RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 Kim B. Heino
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define M41T94_REG_SECONDS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define M41T94_REG_MINUTES 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define M41T94_REG_HOURS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define M41T94_REG_WDAY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define M41T94_REG_DAY 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define M41T94_REG_MONTH 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define M41T94_REG_YEAR 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define M41T94_REG_HT 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define M41T94_BIT_HALT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define M41T94_BIT_STOP 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define M41T94_BIT_CB 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define M41T94_BIT_CEB 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int m41t94_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 buf[8]; /* write cmd + 7 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) dev_dbg(dev, "%s secs=%d, mins=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "write", tm->tm_sec, tm->tm_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) tm->tm_hour, tm->tm_mday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) tm->tm_mon, tm->tm_year, tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) buf[0] = 0x80 | M41T94_REG_SECONDS; /* write time + date */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) buf[M41T94_REG_SECONDS] = bin2bcd(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) buf[M41T94_REG_MINUTES] = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) buf[M41T94_REG_HOURS] = bin2bcd(tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) buf[M41T94_REG_WDAY] = bin2bcd(tm->tm_wday + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) buf[M41T94_REG_DAY] = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) buf[M41T94_REG_MONTH] = bin2bcd(tm->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) buf[M41T94_REG_HOURS] |= M41T94_BIT_CEB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (tm->tm_year >= 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) buf[M41T94_REG_HOURS] |= M41T94_BIT_CB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) buf[M41T94_REG_YEAR] = bin2bcd(tm->tm_year % 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return spi_write(spi, buf, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int m41t94_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int ret, hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* clear halt update bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ret = spi_w8r8(spi, M41T94_REG_HT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (ret & M41T94_BIT_HALT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) buf[0] = 0x80 | M41T94_REG_HT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) buf[1] = ret & ~M41T94_BIT_HALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) spi_write(spi, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* clear stop bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ret = spi_w8r8(spi, M41T94_REG_SECONDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (ret & M41T94_BIT_STOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) buf[0] = 0x80 | M41T94_REG_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) buf[1] = ret & ~M41T94_BIT_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) spi_write(spi, buf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) tm->tm_sec = bcd2bin(spi_w8r8(spi, M41T94_REG_SECONDS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) tm->tm_min = bcd2bin(spi_w8r8(spi, M41T94_REG_MINUTES));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) hour = spi_w8r8(spi, M41T94_REG_HOURS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) tm->tm_hour = bcd2bin(hour & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) tm->tm_wday = bcd2bin(spi_w8r8(spi, M41T94_REG_WDAY)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) tm->tm_mday = bcd2bin(spi_w8r8(spi, M41T94_REG_DAY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) tm->tm_mon = bcd2bin(spi_w8r8(spi, M41T94_REG_MONTH)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) tm->tm_year = bcd2bin(spi_w8r8(spi, M41T94_REG_YEAR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if ((hour & M41T94_BIT_CB) || !(hour & M41T94_BIT_CEB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) tm->tm_year += 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dev_dbg(dev, "%s secs=%d, mins=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) "read", tm->tm_sec, tm->tm_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) tm->tm_hour, tm->tm_mday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) tm->tm_mon, tm->tm_year, tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct rtc_class_ops m41t94_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .read_time = m41t94_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .set_time = m41t94_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct spi_driver m41t94_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int m41t94_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) spi->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) spi_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) res = spi_w8r8(spi, M41T94_REG_SECONDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (res < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dev_err(&spi->dev, "not found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) rtc = devm_rtc_device_register(&spi->dev, m41t94_driver.driver.name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) &m41t94_rtc_ops, THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (IS_ERR(rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return PTR_ERR(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) spi_set_drvdata(spi, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static struct spi_driver m41t94_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .name = "rtc-m41t94",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .probe = m41t94_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) module_spi_driver(m41t94_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MODULE_AUTHOR("Kim B. Heino <Kim.Heino@bluegiga.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MODULE_DESCRIPTION("Driver for ST M41T94 SPI RTC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MODULE_ALIAS("spi:rtc-m41t94");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags