^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2011 Zhao Zhang <zhzhl555@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Derived from driver/rtc/rtc-au1xxx.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <loongson1.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define LS1X_RTC_REG_OFFSET (LS1X_RTC_BASE + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LS1X_RTC_REGS(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) ((void __iomem *)KSEG1ADDR(LS1X_RTC_REG_OFFSET + (x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*RTC programmable counters 0 and 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SYS_COUNTER_CNTRL (LS1X_RTC_REGS(0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SYS_CNTRL_ERS (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SYS_CNTRL_RTS (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SYS_CNTRL_RM2 (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SYS_CNTRL_RM1 (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SYS_CNTRL_RM0 (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SYS_CNTRL_RS (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SYS_CNTRL_BP (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SYS_CNTRL_REN (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SYS_CNTRL_BRT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SYS_CNTRL_TEN (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SYS_CNTRL_BTT (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SYS_CNTRL_E0 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SYS_CNTRL_ETS (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SYS_CNTRL_32S (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SYS_CNTRL_TTS (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SYS_CNTRL_TM2 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SYS_CNTRL_TM1 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SYS_CNTRL_TM0 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SYS_CNTRL_TS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Programmable Counter 0 Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SYS_TOYTRIM (LS1X_RTC_REGS(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SYS_TOYWRITE0 (LS1X_RTC_REGS(4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SYS_TOYWRITE1 (LS1X_RTC_REGS(8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SYS_TOYREAD0 (LS1X_RTC_REGS(0xC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SYS_TOYREAD1 (LS1X_RTC_REGS(0x10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SYS_TOYMATCH0 (LS1X_RTC_REGS(0x14))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SYS_TOYMATCH1 (LS1X_RTC_REGS(0x18))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SYS_TOYMATCH2 (LS1X_RTC_REGS(0x1C))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Programmable Counter 1 Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SYS_RTCTRIM (LS1X_RTC_REGS(0x40))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SYS_RTCWRITE0 (LS1X_RTC_REGS(0x44))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SYS_RTCREAD0 (LS1X_RTC_REGS(0x48))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SYS_RTCMATCH0 (LS1X_RTC_REGS(0x4C))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SYS_RTCMATCH1 (LS1X_RTC_REGS(0x50))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SYS_RTCMATCH2 (LS1X_RTC_REGS(0x54))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LS1X_SEC_OFFSET (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define LS1X_MIN_OFFSET (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define LS1X_HOUR_OFFSET (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LS1X_DAY_OFFSET (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LS1X_MONTH_OFFSET (26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define LS1X_SEC_MASK (0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LS1X_MIN_MASK (0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LS1X_HOUR_MASK (0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define LS1X_DAY_MASK (0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LS1X_MONTH_MASK (0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define LS1X_YEAR_MASK (0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ls1x_get_sec(t) (((t) >> LS1X_SEC_OFFSET) & LS1X_SEC_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ls1x_get_min(t) (((t) >> LS1X_MIN_OFFSET) & LS1X_MIN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ls1x_get_hour(t) (((t) >> LS1X_HOUR_OFFSET) & LS1X_HOUR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ls1x_get_day(t) (((t) >> LS1X_DAY_OFFSET) & LS1X_DAY_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ls1x_get_month(t) (((t) >> LS1X_MONTH_OFFSET) & LS1X_MONTH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RTC_CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int ls1x_rtc_read_time(struct device *dev, struct rtc_time *rtm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned long v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) time64_t t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) v = readl(SYS_TOYREAD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) t = readl(SYS_TOYREAD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) memset(rtm, 0, sizeof(struct rtc_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) t = mktime64((t & LS1X_YEAR_MASK), ls1x_get_month(v),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ls1x_get_day(v), ls1x_get_hour(v),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ls1x_get_min(v), ls1x_get_sec(v));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) rtc_time64_to_tm(t, rtm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int ls1x_rtc_set_time(struct device *dev, struct rtc_time *rtm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned long v, t, c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) v = ((rtm->tm_mon + 1) << LS1X_MONTH_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) | (rtm->tm_mday << LS1X_DAY_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) | (rtm->tm_hour << LS1X_HOUR_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) | (rtm->tm_min << LS1X_MIN_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) | (rtm->tm_sec << LS1X_SEC_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) writel(v, SYS_TOYWRITE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) c = 0x10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* add timeout check counter, for more safe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) while ((readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_TS) && --c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) usleep_range(1000, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (!c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dev_err(dev, "set time timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) t = rtm->tm_year + 1900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) writel(t, SYS_TOYWRITE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) c = 0x10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) while ((readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_TS) && --c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) usleep_range(1000, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (!c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dev_err(dev, "set time timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static const struct rtc_class_ops ls1x_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .read_time = ls1x_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .set_time = ls1x_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int ls1x_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct rtc_device *rtcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned long v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) v = readl(SYS_COUNTER_CNTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (!(v & RTC_CNTR_OK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dev_err(&pdev->dev, "rtc counters not working\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* set to 1 HZ if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (readl(SYS_TOYTRIM) != 32767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) v = 0x100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) while ((readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_TTS) && --v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) usleep_range(1000, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (!v) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dev_err(&pdev->dev, "time out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) writel(32767, SYS_TOYTRIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* this loop coundn't be endless */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_TTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) usleep_range(1000, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) rtcdev = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (IS_ERR(rtcdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return PTR_ERR(rtcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) platform_set_drvdata(pdev, rtcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) rtcdev->ops = &ls1x_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) rtcdev->range_min = RTC_TIMESTAMP_BEGIN_1900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) rtcdev->range_max = RTC_TIMESTAMP_END_2099;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return rtc_register_device(rtcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static struct platform_driver ls1x_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .name = "ls1x-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .probe = ls1x_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) module_platform_driver(ls1x_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MODULE_AUTHOR("zhao zhang <zhzhl555@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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