Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2010 NXP Semiconductors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * Clock and Power control register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define LPC32XX_RTC_UCOUNT		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define LPC32XX_RTC_DCOUNT		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define LPC32XX_RTC_MATCH0		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define LPC32XX_RTC_MATCH1		0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define LPC32XX_RTC_CTRL		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define LPC32XX_RTC_INTSTAT		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define LPC32XX_RTC_KEY			0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define LPC32XX_RTC_SRAM		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define LPC32XX_RTC_CTRL_MATCH0		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define LPC32XX_RTC_CTRL_MATCH1		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define LPC32XX_RTC_CTRL_ONSW_MATCH0	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define LPC32XX_RTC_CTRL_ONSW_MATCH1	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define LPC32XX_RTC_CTRL_SW_RESET	(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define LPC32XX_RTC_CTRL_CNTR_DIS	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define LPC32XX_RTC_CTRL_ONSW_FORCE_HI	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define LPC32XX_RTC_INTSTAT_MATCH0	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define LPC32XX_RTC_INTSTAT_MATCH1	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define LPC32XX_RTC_INTSTAT_ONSW	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define LPC32XX_RTC_KEY_ONSW_LOADVAL	0xB5C13F27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define rtc_readl(dev, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	__raw_readl((dev)->rtc_base + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define rtc_writel(dev, reg, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	__raw_writel((val), (dev)->rtc_base + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) struct lpc32xx_rtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	void __iomem *rtc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	unsigned char alarm_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static int lpc32xx_rtc_read_time(struct device *dev, struct rtc_time *time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	unsigned long elapsed_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	elapsed_sec = rtc_readl(rtc, LPC32XX_RTC_UCOUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	rtc_time64_to_tm(elapsed_sec, time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static int lpc32xx_rtc_set_time(struct device *dev, struct rtc_time *time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	u32 secs = rtc_tm_to_time64(time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	spin_lock_irq(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	/* RTC must be disabled during count update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp | LPC32XX_RTC_CTRL_CNTR_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	rtc_writel(rtc, LPC32XX_RTC_UCOUNT, secs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	rtc_writel(rtc, LPC32XX_RTC_DCOUNT, 0xFFFFFFFF - secs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp &= ~LPC32XX_RTC_CTRL_CNTR_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	spin_unlock_irq(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static int lpc32xx_rtc_read_alarm(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct rtc_wkalrm *wkalrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	rtc_time64_to_tm(rtc_readl(rtc, LPC32XX_RTC_MATCH0), &wkalrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	wkalrm->enabled = rtc->alarm_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	wkalrm->pending = !!(rtc_readl(rtc, LPC32XX_RTC_INTSTAT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		LPC32XX_RTC_INTSTAT_MATCH0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return rtc_valid_tm(&wkalrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static int lpc32xx_rtc_set_alarm(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct rtc_wkalrm *wkalrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	unsigned long alarmsecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	alarmsecs = rtc_tm_to_time64(&wkalrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	spin_lock_irq(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	/* Disable alarm during update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp & ~LPC32XX_RTC_CTRL_MATCH0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	rtc_writel(rtc, LPC32XX_RTC_MATCH0, alarmsecs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	rtc->alarm_enabled = wkalrm->enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	if (wkalrm->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		rtc_writel(rtc, LPC32XX_RTC_INTSTAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			   LPC32XX_RTC_INTSTAT_MATCH0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			   LPC32XX_RTC_CTRL_MATCH0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	spin_unlock_irq(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int lpc32xx_rtc_alarm_irq_enable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	spin_lock_irq(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		rtc->alarm_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		tmp |= LPC32XX_RTC_CTRL_MATCH0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		rtc->alarm_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		tmp &= ~LPC32XX_RTC_CTRL_MATCH0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	spin_unlock_irq(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static irqreturn_t lpc32xx_rtc_alarm_interrupt(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct lpc32xx_rtc *rtc = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	spin_lock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/* Disable alarm interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	rtc_writel(rtc, LPC32XX_RTC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		rtc_readl(rtc, LPC32XX_RTC_CTRL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			  ~LPC32XX_RTC_CTRL_MATCH0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	rtc->alarm_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	 * Write a large value to the match value so the RTC won't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	 * keep firing the match status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	rtc_writel(rtc, LPC32XX_RTC_MATCH0, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	rtc_writel(rtc, LPC32XX_RTC_INTSTAT, LPC32XX_RTC_INTSTAT_MATCH0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	spin_unlock(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const struct rtc_class_ops lpc32xx_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.read_time		= lpc32xx_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.set_time		= lpc32xx_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.read_alarm		= lpc32xx_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.set_alarm		= lpc32xx_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.alarm_irq_enable	= lpc32xx_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int lpc32xx_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct lpc32xx_rtc *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	if (unlikely(!rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	rtc->rtc_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (IS_ERR(rtc->rtc_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		return PTR_ERR(rtc->rtc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	spin_lock_init(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	 * The RTC is on a separate power domain and can keep it's state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	 * across a chip power cycle. If the RTC has never been previously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	 * setup, then set it up now for the first time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (rtc_readl(rtc, LPC32XX_RTC_KEY) != LPC32XX_RTC_KEY_ONSW_LOADVAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		tmp &= ~(LPC32XX_RTC_CTRL_SW_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			LPC32XX_RTC_CTRL_CNTR_DIS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			LPC32XX_RTC_CTRL_MATCH0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			LPC32XX_RTC_CTRL_MATCH1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			LPC32XX_RTC_CTRL_ONSW_MATCH0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			LPC32XX_RTC_CTRL_ONSW_MATCH1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			LPC32XX_RTC_CTRL_ONSW_FORCE_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		/* Clear latched interrupt states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		rtc_writel(rtc, LPC32XX_RTC_MATCH0, 0xFFFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		rtc_writel(rtc, LPC32XX_RTC_INTSTAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			   LPC32XX_RTC_INTSTAT_MATCH0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			   LPC32XX_RTC_INTSTAT_MATCH1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			   LPC32XX_RTC_INTSTAT_ONSW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		/* Write key value to RTC so it won't reload on reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		rtc_writel(rtc, LPC32XX_RTC_KEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			   LPC32XX_RTC_KEY_ONSW_LOADVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		rtc_writel(rtc, LPC32XX_RTC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			   tmp & ~LPC32XX_RTC_CTRL_MATCH0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	platform_set_drvdata(pdev, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (IS_ERR(rtc->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		return PTR_ERR(rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	rtc->rtc->ops = &lpc32xx_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	rtc->rtc->range_max = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	err = rtc_register_device(rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	 * IRQ is enabled after device registration in case alarm IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	 * is pending upon suspend exit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	rtc->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	if (rtc->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		dev_warn(&pdev->dev, "Can't get interrupt resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		if (devm_request_irq(&pdev->dev, rtc->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 				     lpc32xx_rtc_alarm_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 				     0, pdev->name, rtc) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			dev_warn(&pdev->dev, "Can't request interrupt.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			rtc->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int lpc32xx_rtc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (rtc->irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			enable_irq_wake(rtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			disable_irq_wake(rtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int lpc32xx_rtc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (rtc->irq >= 0 && device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		disable_irq_wake(rtc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Unconditionally disable the alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int lpc32xx_rtc_freeze(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	spin_lock_irq(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	rtc_writel(rtc, LPC32XX_RTC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		rtc_readl(rtc, LPC32XX_RTC_CTRL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			  ~LPC32XX_RTC_CTRL_MATCH0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	spin_unlock_irq(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int lpc32xx_rtc_thaw(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	if (rtc->alarm_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		spin_lock_irq(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		rtc_writel(rtc, LPC32XX_RTC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 			   rtc_readl(rtc, LPC32XX_RTC_CTRL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			   LPC32XX_RTC_CTRL_MATCH0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		spin_unlock_irq(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const struct dev_pm_ops lpc32xx_rtc_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	.suspend = lpc32xx_rtc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.resume = lpc32xx_rtc_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.freeze = lpc32xx_rtc_freeze,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.thaw = lpc32xx_rtc_thaw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.restore = lpc32xx_rtc_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define LPC32XX_RTC_PM_OPS (&lpc32xx_rtc_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define LPC32XX_RTC_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const struct of_device_id lpc32xx_rtc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	{ .compatible = "nxp,lpc3220-rtc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MODULE_DEVICE_TABLE(of, lpc32xx_rtc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static struct platform_driver lpc32xx_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	.probe		= lpc32xx_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		.name	= "rtc-lpc32xx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		.pm	= LPC32XX_RTC_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		.of_match_table = of_match_ptr(lpc32xx_rtc_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) module_platform_driver(lpc32xx_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) MODULE_AUTHOR("Kevin Wells <wellsk40@gmail.com");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MODULE_DESCRIPTION("RTC driver for the LPC32xx SoC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MODULE_ALIAS("platform:rtc-lpc32xx");