^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * RTC driver for NXP LPC178x/18xx/43xx Real-Time Clock (RTC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011 NXP Semiconductors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* LPC24xx RTC register offsets and bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LPC24XX_ILR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LPC24XX_RTCCIF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LPC24XX_RTCALF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LPC24XX_CTC 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LPC24XX_CCR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LPC24XX_CLKEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LPC178X_CCALEN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LPC24XX_CIIR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LPC24XX_AMR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LPC24XX_ALARM_DISABLE 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LPC24XX_CTIME0 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LPC24XX_CTIME1 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LPC24XX_CTIME2 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LPC24XX_SEC 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LPC24XX_MIN 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LPC24XX_HOUR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LPC24XX_DOM 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LPC24XX_DOW 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LPC24XX_DOY 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LPC24XX_MONTH 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LPC24XX_YEAR 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LPC24XX_ALSEC 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LPC24XX_ALMIN 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LPC24XX_ALHOUR 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LPC24XX_ALDOM 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LPC24XX_ALDOW 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LPC24XX_ALDOY 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LPC24XX_ALMON 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LPC24XX_ALYEAR 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Macros to read fields in consolidated time (CT) registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CT0_SECS(x) (((x) >> 0) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CT0_MINS(x) (((x) >> 8) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CT0_HOURS(x) (((x) >> 16) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CT0_DOW(x) (((x) >> 24) & 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CT1_DOM(x) (((x) >> 0) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CT1_MONTH(x) (((x) >> 8) & 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CT1_YEAR(x) (((x) >> 16) & 0xfff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CT2_DOY(x) (((x) >> 0) & 0xfff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define rtc_readl(dev, reg) readl((dev)->rtc_base + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define rtc_writel(dev, reg, val) writel((val), (dev)->rtc_base + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct lpc24xx_rtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) void __iomem *rtc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct clk *clk_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct clk *clk_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int lpc24xx_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct lpc24xx_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Disable RTC during update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) rtc_writel(rtc, LPC24XX_CCR, LPC178X_CCALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) rtc_writel(rtc, LPC24XX_SEC, tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) rtc_writel(rtc, LPC24XX_MIN, tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) rtc_writel(rtc, LPC24XX_HOUR, tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) rtc_writel(rtc, LPC24XX_DOW, tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) rtc_writel(rtc, LPC24XX_DOM, tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) rtc_writel(rtc, LPC24XX_DOY, tm->tm_yday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) rtc_writel(rtc, LPC24XX_MONTH, tm->tm_mon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) rtc_writel(rtc, LPC24XX_YEAR, tm->tm_year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) rtc_writel(rtc, LPC24XX_CCR, LPC24XX_CLKEN | LPC178X_CCALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int lpc24xx_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct lpc24xx_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 ct0, ct1, ct2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ct0 = rtc_readl(rtc, LPC24XX_CTIME0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ct1 = rtc_readl(rtc, LPC24XX_CTIME1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ct2 = rtc_readl(rtc, LPC24XX_CTIME2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) tm->tm_sec = CT0_SECS(ct0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) tm->tm_min = CT0_MINS(ct0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) tm->tm_hour = CT0_HOURS(ct0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) tm->tm_wday = CT0_DOW(ct0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) tm->tm_mon = CT1_MONTH(ct1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) tm->tm_mday = CT1_DOM(ct1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) tm->tm_year = CT1_YEAR(ct1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) tm->tm_yday = CT2_DOY(ct2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int lpc24xx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct lpc24xx_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct rtc_time *tm = &wkalrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) tm->tm_sec = rtc_readl(rtc, LPC24XX_ALSEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) tm->tm_min = rtc_readl(rtc, LPC24XX_ALMIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) tm->tm_hour = rtc_readl(rtc, LPC24XX_ALHOUR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) tm->tm_mday = rtc_readl(rtc, LPC24XX_ALDOM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) tm->tm_wday = rtc_readl(rtc, LPC24XX_ALDOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) tm->tm_yday = rtc_readl(rtc, LPC24XX_ALDOY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) tm->tm_mon = rtc_readl(rtc, LPC24XX_ALMON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) tm->tm_year = rtc_readl(rtc, LPC24XX_ALYEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) wkalrm->enabled = rtc_readl(rtc, LPC24XX_AMR) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) wkalrm->pending = !!(rtc_readl(rtc, LPC24XX_ILR) & LPC24XX_RTCCIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return rtc_valid_tm(&wkalrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int lpc24xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct lpc24xx_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct rtc_time *tm = &wkalrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Disable alarm irq during update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) rtc_writel(rtc, LPC24XX_AMR, LPC24XX_ALARM_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) rtc_writel(rtc, LPC24XX_ALSEC, tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) rtc_writel(rtc, LPC24XX_ALMIN, tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) rtc_writel(rtc, LPC24XX_ALHOUR, tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) rtc_writel(rtc, LPC24XX_ALDOM, tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) rtc_writel(rtc, LPC24XX_ALDOW, tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) rtc_writel(rtc, LPC24XX_ALDOY, tm->tm_yday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) rtc_writel(rtc, LPC24XX_ALMON, tm->tm_mon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) rtc_writel(rtc, LPC24XX_ALYEAR, tm->tm_year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (wkalrm->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) rtc_writel(rtc, LPC24XX_AMR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int lpc24xx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct lpc24xx_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) rtc_writel(rtc, LPC24XX_AMR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) rtc_writel(rtc, LPC24XX_AMR, LPC24XX_ALARM_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static irqreturn_t lpc24xx_rtc_interrupt(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned long events = RTC_IRQF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct lpc24xx_rtc *rtc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 rtc_iir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Check interrupt cause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) rtc_iir = rtc_readl(rtc, LPC24XX_ILR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (rtc_iir & LPC24XX_RTCALF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) events |= RTC_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) rtc_writel(rtc, LPC24XX_AMR, LPC24XX_ALARM_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Clear interrupt status and report event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) rtc_writel(rtc, LPC24XX_ILR, rtc_iir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) rtc_update_irq(rtc->rtc, 1, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const struct rtc_class_ops lpc24xx_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .read_time = lpc24xx_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .set_time = lpc24xx_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .read_alarm = lpc24xx_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .set_alarm = lpc24xx_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .alarm_irq_enable = lpc24xx_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int lpc24xx_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct lpc24xx_rtc *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (!rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) rtc->rtc_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (IS_ERR(rtc->rtc_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return PTR_ERR(rtc->rtc_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) rtc->clk_rtc = devm_clk_get(&pdev->dev, "rtc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (IS_ERR(rtc->clk_rtc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dev_err(&pdev->dev, "error getting rtc clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return PTR_ERR(rtc->clk_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) rtc->clk_reg = devm_clk_get(&pdev->dev, "reg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (IS_ERR(rtc->clk_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dev_err(&pdev->dev, "error getting reg clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return PTR_ERR(rtc->clk_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ret = clk_prepare_enable(rtc->clk_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_err(&pdev->dev, "unable to enable rtc clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ret = clk_prepare_enable(rtc->clk_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dev_err(&pdev->dev, "unable to enable reg clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) goto disable_rtc_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) platform_set_drvdata(pdev, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Clear any pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) rtc_writel(rtc, LPC24XX_ILR, LPC24XX_RTCCIF | LPC24XX_RTCALF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Enable RTC count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) rtc_writel(rtc, LPC24XX_CCR, LPC24XX_CLKEN | LPC178X_CCALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = devm_request_irq(&pdev->dev, irq, lpc24xx_rtc_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pdev->name, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dev_warn(&pdev->dev, "can't request interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) goto disable_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) rtc->rtc = devm_rtc_device_register(&pdev->dev, "lpc24xx-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) &lpc24xx_rtc_ops, THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (IS_ERR(rtc->rtc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dev_err(&pdev->dev, "can't register rtc device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ret = PTR_ERR(rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) goto disable_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) disable_clks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) clk_disable_unprepare(rtc->clk_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) disable_rtc_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) clk_disable_unprepare(rtc->clk_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int lpc24xx_rtc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct lpc24xx_rtc *rtc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Ensure all interrupt sources are masked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) rtc_writel(rtc, LPC24XX_AMR, LPC24XX_ALARM_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) rtc_writel(rtc, LPC24XX_CIIR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) rtc_writel(rtc, LPC24XX_CCR, LPC178X_CCALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) clk_disable_unprepare(rtc->clk_rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) clk_disable_unprepare(rtc->clk_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static const struct of_device_id lpc24xx_rtc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { .compatible = "nxp,lpc1788-rtc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MODULE_DEVICE_TABLE(of, lpc24xx_rtc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static struct platform_driver lpc24xx_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .probe = lpc24xx_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .remove = lpc24xx_rtc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .name = "lpc24xx-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .of_match_table = lpc24xx_rtc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) module_platform_driver(lpc24xx_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MODULE_AUTHOR("Kevin Wells <wellsk40@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MODULE_DESCRIPTION("RTC driver for the LPC178x/18xx/408x/43xx SoCs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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