Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *	 JZ4740 SoC RTC driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/pm_wakeirq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define JZ_REG_RTC_CTRL		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define JZ_REG_RTC_SEC		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define JZ_REG_RTC_SEC_ALARM	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define JZ_REG_RTC_REGULATOR	0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define JZ_REG_RTC_HIBERNATE	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define JZ_REG_RTC_WAKEUP_FILTER	0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define JZ_REG_RTC_RESET_COUNTER	0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define JZ_REG_RTC_SCRATCHPAD	0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* The following are present on the jz4780 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define JZ_REG_RTC_WENR	0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define JZ_RTC_WENR_WEN	BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define JZ_RTC_CTRL_WRDY	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define JZ_RTC_CTRL_1HZ		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define JZ_RTC_CTRL_1HZ_IRQ	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define JZ_RTC_CTRL_AF		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define JZ_RTC_CTRL_AF_IRQ	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define JZ_RTC_CTRL_AE		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define JZ_RTC_CTRL_ENABLE	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* Magic value to enable writes on jz4780 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define JZ_RTC_WENR_MAGIC	0xA55A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define JZ_RTC_WAKEUP_FILTER_MASK	0x0000FFE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define JZ_RTC_RESET_COUNTER_MASK	0x00000FE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) enum jz4740_rtc_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	ID_JZ4740,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	ID_JZ4760,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	ID_JZ4780,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) struct jz4740_rtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	enum jz4740_rtc_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static struct device *dev_for_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	return readl(rtc->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	uint32_t ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	int timeout = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	} while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	return timeout ? 0 : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static inline int jz4780_rtc_enable_write(struct jz4740_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	uint32_t ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	int ret, timeout = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	ret = jz4740_rtc_wait_write_ready(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		ctrl = readl(rtc->base + JZ_REG_RTC_WENR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	} while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return timeout ? 0 : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	uint32_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if (rtc->type >= ID_JZ4760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		ret = jz4780_rtc_enable_write(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		ret = jz4740_rtc_wait_write_ready(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		writel(val, rtc->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	uint32_t ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	spin_lock_irqsave(&rtc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/* Don't clear interrupt flags by accident */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		ctrl |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		ctrl &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	spin_unlock_irqrestore(&rtc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	uint32_t secs, secs2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	int timeout = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD) != 0x12345678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	/* If the seconds register is read while it is updated, it can contain a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	 * bogus value. This can be avoided by making sure that two consecutive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	 * reads have the same value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	while (secs != secs2 && --timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		secs = secs2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	rtc_time64_to_tm(secs, time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int jz4740_rtc_set_time(struct device *dev, struct rtc_time *time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, rtc_tm_to_time64(time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	uint32_t secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	uint32_t ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	rtc_time64_to_tm(secs, &alrm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	uint32_t secs = lower_32_bits(rtc_tm_to_time64(&alrm->time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		ret = jz4740_rtc_ctrl_set_bits(rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			JZ_RTC_CTRL_AE | JZ_RTC_CTRL_AF_IRQ, alrm->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const struct rtc_class_ops jz4740_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.read_time	= jz4740_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.set_time	= jz4740_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.read_alarm	= jz4740_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	.set_alarm	= jz4740_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	.alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static irqreturn_t jz4740_rtc_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	struct jz4740_rtc *rtc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	uint32_t ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	unsigned long events = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (ctrl & JZ_RTC_CTRL_1HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		events |= (RTC_UF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (ctrl & JZ_RTC_CTRL_AF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		events |= (RTC_AF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	rtc_update_irq(rtc->rtc, 1, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static void jz4740_rtc_poweroff(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	struct jz4740_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static void jz4740_rtc_power_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	jz4740_rtc_poweroff(dev_for_power_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	kernel_halt();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static void jz4740_rtc_clk_disable(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	clk_disable_unprepare(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct of_device_id jz4740_rtc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	{ .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	{ .compatible = "ingenic,jz4760-rtc", .data = (void *)ID_JZ4760 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	{ .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MODULE_DEVICE_TABLE(of, jz4740_rtc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static void jz4740_rtc_set_wakeup_params(struct jz4740_rtc *rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 					 struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 					 unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	unsigned long wakeup_ticks, reset_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	unsigned int min_wakeup_pin_assert_time = 60; /* Default: 60ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	unsigned int reset_pin_assert_time = 100; /* Default: 100ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	of_property_read_u32(np, "ingenic,reset-pin-assert-time-ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 			     &reset_pin_assert_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	of_property_read_u32(np, "ingenic,min-wakeup-pin-assert-time-ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			     &min_wakeup_pin_assert_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	 * Set minimum wakeup pin assertion time: 100 ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	 * Range is 0 to 2 sec if RTC is clocked at 32 kHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	wakeup_ticks = (min_wakeup_pin_assert_time * rate) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (wakeup_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		wakeup_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		wakeup_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_WAKEUP_FILTER, wakeup_ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	 * Set reset pin low-level assertion time after wakeup: 60 ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	 * Range is 0 to 125 ms if RTC is clocked at 32 kHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	reset_ticks = (reset_pin_assert_time * rate) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (reset_ticks < JZ_RTC_RESET_COUNTER_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		reset_ticks &= JZ_RTC_RESET_COUNTER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		reset_ticks = JZ_RTC_RESET_COUNTER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_RESET_COUNTER, reset_ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int jz4740_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	struct jz4740_rtc *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	if (!rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	rtc->type = (enum jz4740_rtc_type)device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	rtc->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	if (IS_ERR(rtc->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		return PTR_ERR(rtc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	clk = devm_clk_get(dev, "rtc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		dev_err(dev, "Failed to get RTC clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		dev_err(dev, "Failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	ret = devm_add_action_or_reset(dev, jz4740_rtc_clk_disable, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		dev_err(dev, "Failed to register devm action\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	spin_lock_init(&rtc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	platform_set_drvdata(pdev, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	device_init_wakeup(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	ret = dev_pm_set_wake_irq(dev, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		dev_err(dev, "Failed to set wake irq: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	rtc->rtc = devm_rtc_allocate_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	if (IS_ERR(rtc->rtc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		ret = PTR_ERR(rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		dev_err(dev, "Failed to allocate rtc device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	rtc->rtc->ops = &jz4740_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	rtc->rtc->range_max = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	jz4740_rtc_set_wakeup_params(rtc, np, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	/* Each 1 Hz pulse should happen after (rate) ticks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_REGULATOR, rate - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	ret = rtc_register_device(rtc->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	ret = devm_request_irq(dev, irq, jz4740_rtc_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 			       pdev->name, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		dev_err(dev, "Failed to request rtc irq: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	if (of_device_is_system_power_controller(np)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		dev_for_power_off = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		if (!pm_power_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 			pm_power_off = jz4740_rtc_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 			dev_warn(dev, "Poweroff handler already present!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static struct platform_driver jz4740_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	.probe	 = jz4740_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	.driver	 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		.name  = "jz4740-rtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		.of_match_table = jz4740_rtc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) module_platform_driver(jz4740_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MODULE_ALIAS("platform:jz4740-rtc");