^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intersil ISL1208 rtc class driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2005,2006 Hebert Valerio Riedel <hvr@gnu.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Register map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* rtc section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ISL1208_REG_SC 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ISL1208_REG_MN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ISL1208_REG_HR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ISL1208_REG_HR_MIL (1<<7) /* 24h/12h mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ISL1208_REG_HR_PM (1<<5) /* PM/AM bit in 12h mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ISL1208_REG_DT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ISL1208_REG_MO 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ISL1208_REG_YR 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ISL1208_REG_DW 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ISL1208_RTC_SECTION_LEN 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* control/status section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ISL1208_REG_SR 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ISL1208_REG_SR_ARST (1<<7) /* auto reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ISL1208_REG_SR_XTOSCB (1<<6) /* crystal oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ISL1208_REG_SR_WRTC (1<<4) /* write rtc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ISL1208_REG_SR_EVT (1<<3) /* event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ISL1208_REG_SR_ALM (1<<2) /* alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ISL1208_REG_SR_BAT (1<<1) /* battery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ISL1208_REG_SR_RTCF (1<<0) /* rtc fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ISL1208_REG_INT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ISL1208_REG_INT_ALME (1<<6) /* alarm enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ISL1208_REG_INT_IM (1<<7) /* interrupt/alarm mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ISL1219_REG_EV 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ISL1219_REG_EV_EVEN (1<<4) /* event detection enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ISL1219_REG_EV_EVIENB (1<<7) /* event in pull-up disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ISL1208_REG_ATR 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ISL1208_REG_DTR 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* alarm section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ISL1208_REG_SCA 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ISL1208_REG_MNA 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ISL1208_REG_HRA 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ISL1208_REG_DTA 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ISL1208_REG_MOA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ISL1208_REG_DWA 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ISL1208_ALARM_SECTION_LEN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* user section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ISL1208_REG_USR1 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ISL1208_REG_USR2 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ISL1208_USR_SECTION_LEN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* event section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ISL1219_REG_SCT 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ISL1219_REG_MNT 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ISL1219_REG_HRT 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ISL1219_REG_DTT 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ISL1219_REG_MOT 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ISL1219_REG_YRT 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ISL1219_EVT_SECTION_LEN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static struct i2c_driver isl1208_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* ISL1208 various variants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) enum isl1208_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) TYPE_ISL1208 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) TYPE_ISL1209,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) TYPE_ISL1218,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) TYPE_ISL1219,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ISL_LAST_ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Chip capabilities table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const struct isl1208_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const char name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int nvmem_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned has_tamper:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned has_timestamp:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) } isl1208_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) [TYPE_ISL1208] = { "isl1208", 2, false, false },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) [TYPE_ISL1209] = { "isl1209", 2, true, false },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) [TYPE_ISL1218] = { "isl1218", 8, false, false },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [TYPE_ISL1219] = { "isl1219", 2, true, true },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static const struct i2c_device_id isl1208_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { "isl1208", TYPE_ISL1208 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { "isl1209", TYPE_ISL1209 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { "isl1218", TYPE_ISL1218 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { "isl1219", TYPE_ISL1219 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MODULE_DEVICE_TABLE(i2c, isl1208_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct of_device_id isl1208_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { .compatible = "isil,isl1208", .data = &isl1208_configs[TYPE_ISL1208] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { .compatible = "isil,isl1209", .data = &isl1208_configs[TYPE_ISL1209] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { .compatible = "isil,isl1218", .data = &isl1208_configs[TYPE_ISL1218] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { .compatible = "isil,isl1219", .data = &isl1208_configs[TYPE_ISL1219] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MODULE_DEVICE_TABLE(of, isl1208_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Device state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct isl1208_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct nvmem_config nvmem_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) const struct isl1208_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* block read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) isl1208_i2c_read_regs(struct i2c_client *client, u8 reg, u8 buf[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) WARN_ON(reg > ISL1219_REG_YRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) WARN_ON(reg + len > ISL1219_REG_YRT + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ret = i2c_smbus_read_i2c_block_data(client, reg, len, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return (ret < 0) ? ret : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* block write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) isl1208_i2c_set_regs(struct i2c_client *client, u8 reg, u8 const buf[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) WARN_ON(reg > ISL1219_REG_YRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) WARN_ON(reg + len > ISL1219_REG_YRT + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ret = i2c_smbus_write_i2c_block_data(client, reg, len, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return (ret < 0) ? ret : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* simple check to see whether we have a isl1208 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) isl1208_i2c_validate_client(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u8 regs[ISL1208_RTC_SECTION_LEN] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u8 zero_mask[ISL1208_RTC_SECTION_LEN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 0x80, 0x80, 0x40, 0xc0, 0xe0, 0x00, 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = isl1208_i2c_read_regs(client, 0, regs, ISL1208_RTC_SECTION_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) for (i = 0; i < ISL1208_RTC_SECTION_LEN; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (regs[i] & zero_mask[i]) /* check if bits are cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) isl1208_i2c_get_sr(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return i2c_smbus_read_byte_data(client, ISL1208_REG_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) isl1208_i2c_get_atr(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int atr = i2c_smbus_read_byte_data(client, ISL1208_REG_ATR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (atr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return atr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* The 6bit value in the ATR register controls the load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * capacitance C_load * in steps of 0.25pF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * bit (1<<5) of the ATR register is inverted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * C_load(ATR=0x20) = 4.50pF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * C_load(ATR=0x00) = 12.50pF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * C_load(ATR=0x1f) = 20.25pF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) atr &= 0x3f; /* mask out lsb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) atr ^= 1 << 5; /* invert 6th bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) atr += 2 * 9; /* add offset of 4.5pF; unit[atr] = 0.25pF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return atr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* returns adjustment value + 100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) isl1208_i2c_get_dtr(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int dtr = i2c_smbus_read_byte_data(client, ISL1208_REG_DTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (dtr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* dtr encodes adjustments of {-60,-40,-20,0,20,40,60} ppm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dtr = ((dtr & 0x3) * 20) * (dtr & (1 << 2) ? -1 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return dtr + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) isl1208_i2c_get_usr(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u8 buf[ISL1208_USR_SECTION_LEN] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = isl1208_i2c_read_regs(client, ISL1208_REG_USR1, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ISL1208_USR_SECTION_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return (buf[1] << 8) | buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) isl1208_i2c_set_usr(struct i2c_client *client, u16 usr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u8 buf[ISL1208_USR_SECTION_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) buf[0] = usr & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) buf[1] = (usr >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return isl1208_i2c_set_regs(client, ISL1208_REG_USR1, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ISL1208_USR_SECTION_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) isl1208_rtc_toggle_alarm(struct i2c_client *client, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int icr = i2c_smbus_read_byte_data(client, ISL1208_REG_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (icr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dev_err(&client->dev, "%s: reading INT failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return icr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) icr |= ISL1208_REG_INT_ALME | ISL1208_REG_INT_IM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) icr &= ~(ISL1208_REG_INT_ALME | ISL1208_REG_INT_IM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) icr = i2c_smbus_write_byte_data(client, ISL1208_REG_INT, icr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (icr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_err(&client->dev, "%s: writing INT failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return icr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) isl1208_rtc_proc(struct device *dev, struct seq_file *seq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct i2c_client *const client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int sr, dtr, atr, usr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) sr = isl1208_i2c_get_sr(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (sr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dev_err(&client->dev, "%s: reading SR failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) seq_printf(seq, "status_reg\t:%s%s%s%s%s%s (0x%.2x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) (sr & ISL1208_REG_SR_RTCF) ? " RTCF" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) (sr & ISL1208_REG_SR_BAT) ? " BAT" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) (sr & ISL1208_REG_SR_ALM) ? " ALM" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) (sr & ISL1208_REG_SR_WRTC) ? " WRTC" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) (sr & ISL1208_REG_SR_XTOSCB) ? " XTOSCB" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) (sr & ISL1208_REG_SR_ARST) ? " ARST" : "", sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) seq_printf(seq, "batt_status\t: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) (sr & ISL1208_REG_SR_RTCF) ? "bad" : "okay");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dtr = isl1208_i2c_get_dtr(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (dtr >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) seq_printf(seq, "digital_trim\t: %d ppm\n", dtr - 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) atr = isl1208_i2c_get_atr(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (atr >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) seq_printf(seq, "analog_trim\t: %d.%.2d pF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) atr >> 2, (atr & 0x3) * 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) usr = isl1208_i2c_get_usr(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (usr >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) seq_printf(seq, "user_data\t: 0x%.4x\n", usr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) isl1208_i2c_read_time(struct i2c_client *client, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u8 regs[ISL1208_RTC_SECTION_LEN] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) sr = isl1208_i2c_get_sr(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (sr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) dev_err(&client->dev, "%s: reading SR failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) sr = isl1208_i2c_read_regs(client, 0, regs, ISL1208_RTC_SECTION_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (sr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dev_err(&client->dev, "%s: reading RTC section failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) tm->tm_sec = bcd2bin(regs[ISL1208_REG_SC]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) tm->tm_min = bcd2bin(regs[ISL1208_REG_MN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* HR field has a more complex interpretation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) const u8 _hr = regs[ISL1208_REG_HR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (_hr & ISL1208_REG_HR_MIL) /* 24h format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) tm->tm_hour = bcd2bin(_hr & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* 12h format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) tm->tm_hour = bcd2bin(_hr & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (_hr & ISL1208_REG_HR_PM) /* PM flag set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) tm->tm_hour += 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) tm->tm_mday = bcd2bin(regs[ISL1208_REG_DT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) tm->tm_mon = bcd2bin(regs[ISL1208_REG_MO]) - 1; /* rtc starts at 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) tm->tm_year = bcd2bin(regs[ISL1208_REG_YR]) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) tm->tm_wday = bcd2bin(regs[ISL1208_REG_DW]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) isl1208_i2c_read_alarm(struct i2c_client *client, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct rtc_time *const tm = &alarm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u8 regs[ISL1208_ALARM_SECTION_LEN] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int icr, yr, sr = isl1208_i2c_get_sr(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (sr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dev_err(&client->dev, "%s: reading SR failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) sr = isl1208_i2c_read_regs(client, ISL1208_REG_SCA, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ISL1208_ALARM_SECTION_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (sr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dev_err(&client->dev, "%s: reading alarm section failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* MSB of each alarm register is an enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) tm->tm_sec = bcd2bin(regs[ISL1208_REG_SCA - ISL1208_REG_SCA] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) tm->tm_min = bcd2bin(regs[ISL1208_REG_MNA - ISL1208_REG_SCA] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) tm->tm_hour = bcd2bin(regs[ISL1208_REG_HRA - ISL1208_REG_SCA] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) tm->tm_mday = bcd2bin(regs[ISL1208_REG_DTA - ISL1208_REG_SCA] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) tm->tm_mon =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) bcd2bin(regs[ISL1208_REG_MOA - ISL1208_REG_SCA] & 0x1f) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) tm->tm_wday = bcd2bin(regs[ISL1208_REG_DWA - ISL1208_REG_SCA] & 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* The alarm doesn't store the year so get it from the rtc section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) yr = i2c_smbus_read_byte_data(client, ISL1208_REG_YR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (yr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_err(&client->dev, "%s: reading RTC YR failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return yr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) tm->tm_year = bcd2bin(yr) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) icr = i2c_smbus_read_byte_data(client, ISL1208_REG_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (icr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dev_err(&client->dev, "%s: reading INT failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return icr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) alarm->enabled = !!(icr & ISL1208_REG_INT_ALME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) isl1208_i2c_set_alarm(struct i2c_client *client, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct rtc_time *alarm_tm = &alarm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u8 regs[ISL1208_ALARM_SECTION_LEN] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) const int offs = ISL1208_REG_SCA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct rtc_time rtc_tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int err, enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) err = isl1208_i2c_read_time(client, &rtc_tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* If the alarm time is before the current time disable the alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (!alarm->enabled || rtc_tm_sub(alarm_tm, &rtc_tm) <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) enable = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) enable = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* Program the alarm and enable it for each setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) regs[ISL1208_REG_SCA - offs] = bin2bcd(alarm_tm->tm_sec) | enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) regs[ISL1208_REG_MNA - offs] = bin2bcd(alarm_tm->tm_min) | enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) regs[ISL1208_REG_HRA - offs] = bin2bcd(alarm_tm->tm_hour) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ISL1208_REG_HR_MIL | enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) regs[ISL1208_REG_DTA - offs] = bin2bcd(alarm_tm->tm_mday) | enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) regs[ISL1208_REG_MOA - offs] = bin2bcd(alarm_tm->tm_mon + 1) | enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) regs[ISL1208_REG_DWA - offs] = bin2bcd(alarm_tm->tm_wday & 7) | enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* write ALARM registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) err = isl1208_i2c_set_regs(client, offs, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ISL1208_ALARM_SECTION_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) dev_err(&client->dev, "%s: writing ALARM section failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) err = isl1208_rtc_toggle_alarm(client, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) isl1208_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return isl1208_i2c_read_time(to_i2c_client(dev), tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) isl1208_i2c_set_time(struct i2c_client *client, struct rtc_time const *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u8 regs[ISL1208_RTC_SECTION_LEN] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* The clock has an 8 bit wide bcd-coded register (they never learn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * for the year. tm_year is an offset from 1900 and we are interested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * in the 2000-2099 range, so any value less than 100 is invalid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (tm->tm_year < 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) regs[ISL1208_REG_SC] = bin2bcd(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) regs[ISL1208_REG_MN] = bin2bcd(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) regs[ISL1208_REG_HR] = bin2bcd(tm->tm_hour) | ISL1208_REG_HR_MIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) regs[ISL1208_REG_DT] = bin2bcd(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) regs[ISL1208_REG_MO] = bin2bcd(tm->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) regs[ISL1208_REG_YR] = bin2bcd(tm->tm_year - 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) regs[ISL1208_REG_DW] = bin2bcd(tm->tm_wday & 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) sr = isl1208_i2c_get_sr(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (sr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dev_err(&client->dev, "%s: reading SR failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* set WRTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) sr = i2c_smbus_write_byte_data(client, ISL1208_REG_SR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) sr | ISL1208_REG_SR_WRTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (sr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_err(&client->dev, "%s: writing SR failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* write RTC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) sr = isl1208_i2c_set_regs(client, 0, regs, ISL1208_RTC_SECTION_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (sr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dev_err(&client->dev, "%s: writing RTC section failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* clear WRTC again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) sr = isl1208_i2c_get_sr(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (sr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev_err(&client->dev, "%s: reading SR failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) sr = i2c_smbus_write_byte_data(client, ISL1208_REG_SR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) sr & ~ISL1208_REG_SR_WRTC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (sr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) dev_err(&client->dev, "%s: writing SR failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) isl1208_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return isl1208_i2c_set_time(to_i2c_client(dev), tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) isl1208_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return isl1208_i2c_read_alarm(to_i2c_client(dev), alarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) isl1208_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return isl1208_i2c_set_alarm(to_i2c_client(dev), alarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static ssize_t timestamp0_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct i2c_client *client = to_i2c_client(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) sr = isl1208_i2c_get_sr(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (sr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dev_err(dev, "%s: reading SR failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) sr &= ~ISL1208_REG_SR_EVT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) sr = i2c_smbus_write_byte_data(client, ISL1208_REG_SR, sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (sr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dev_err(dev, "%s: writing SR failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static ssize_t timestamp0_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct i2c_client *client = to_i2c_client(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u8 regs[ISL1219_EVT_SECTION_LEN] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct rtc_time tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) sr = isl1208_i2c_get_sr(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (sr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev_err(dev, "%s: reading SR failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (!(sr & ISL1208_REG_SR_EVT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) sr = isl1208_i2c_read_regs(client, ISL1219_REG_SCT, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ISL1219_EVT_SECTION_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (sr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dev_err(dev, "%s: reading event section failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* MSB of each alarm register is an enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) tm.tm_sec = bcd2bin(regs[ISL1219_REG_SCT - ISL1219_REG_SCT] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) tm.tm_min = bcd2bin(regs[ISL1219_REG_MNT - ISL1219_REG_SCT] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) tm.tm_hour = bcd2bin(regs[ISL1219_REG_HRT - ISL1219_REG_SCT] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) tm.tm_mday = bcd2bin(regs[ISL1219_REG_DTT - ISL1219_REG_SCT] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) tm.tm_mon =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) bcd2bin(regs[ISL1219_REG_MOT - ISL1219_REG_SCT] & 0x1f) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) tm.tm_year = bcd2bin(regs[ISL1219_REG_YRT - ISL1219_REG_SCT]) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) sr = rtc_valid_tm(&tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (sr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return sprintf(buf, "%llu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) (unsigned long long)rtc_tm_to_time64(&tm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static DEVICE_ATTR_RW(timestamp0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) isl1208_rtc_interrupt(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) unsigned long timeout = jiffies + msecs_to_jiffies(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct i2c_client *client = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct isl1208_state *isl1208 = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) int handled = 0, sr, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * I2C reads get NAK'ed if we read straight away after an interrupt?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * Using a mdelay/msleep didn't seem to help either, so we work around
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * this by continually trying to read the register for a short time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) sr = isl1208_i2c_get_sr(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (sr >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dev_err(&client->dev, "%s: reading SR failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (sr & ISL1208_REG_SR_ALM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) dev_dbg(&client->dev, "alarm!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) rtc_update_irq(isl1208->rtc, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* Clear the alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) sr &= ~ISL1208_REG_SR_ALM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) sr = i2c_smbus_write_byte_data(client, ISL1208_REG_SR, sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (sr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) dev_err(&client->dev, "%s: writing SR failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* Disable the alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) err = isl1208_rtc_toggle_alarm(client, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (isl1208->config->has_tamper && (sr & ISL1208_REG_SR_EVT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) dev_warn(&client->dev, "event detected");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (isl1208->config->has_timestamp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) sysfs_notify(&isl1208->rtc->dev.kobj, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dev_attr_timestamp0.attr.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return handled ? IRQ_HANDLED : IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static const struct rtc_class_ops isl1208_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .proc = isl1208_rtc_proc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .read_time = isl1208_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .set_time = isl1208_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .read_alarm = isl1208_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .set_alarm = isl1208_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* sysfs interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) isl1208_sysfs_show_atrim(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) int atr = isl1208_i2c_get_atr(to_i2c_client(dev->parent));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (atr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return atr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return sprintf(buf, "%d.%.2d pF\n", atr >> 2, (atr & 0x3) * 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static DEVICE_ATTR(atrim, S_IRUGO, isl1208_sysfs_show_atrim, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) isl1208_sysfs_show_dtrim(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) int dtr = isl1208_i2c_get_dtr(to_i2c_client(dev->parent));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (dtr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return dtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return sprintf(buf, "%d ppm\n", dtr - 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static DEVICE_ATTR(dtrim, S_IRUGO, isl1208_sysfs_show_dtrim, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) isl1208_sysfs_show_usr(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) int usr = isl1208_i2c_get_usr(to_i2c_client(dev->parent));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (usr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return usr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return sprintf(buf, "0x%.4x\n", usr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) isl1208_sysfs_store_usr(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) int usr = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (buf[0] == '0' && (buf[1] == 'x' || buf[1] == 'X')) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (sscanf(buf, "%x", &usr) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (sscanf(buf, "%d", &usr) != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (usr < 0 || usr > 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (isl1208_i2c_set_usr(to_i2c_client(dev->parent), usr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static DEVICE_ATTR(usr, S_IRUGO | S_IWUSR, isl1208_sysfs_show_usr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) isl1208_sysfs_store_usr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static struct attribute *isl1208_rtc_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) &dev_attr_atrim.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) &dev_attr_dtrim.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) &dev_attr_usr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static const struct attribute_group isl1208_rtc_sysfs_files = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .attrs = isl1208_rtc_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static struct attribute *isl1219_rtc_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) &dev_attr_timestamp0.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static const struct attribute_group isl1219_rtc_sysfs_files = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .attrs = isl1219_rtc_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static int isl1208_nvmem_read(void *priv, unsigned int off, void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct isl1208_state *isl1208 = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct i2c_client *client = to_i2c_client(isl1208->rtc->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* nvmem sanitizes offset/count for us, but count==0 is possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (!count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ret = isl1208_i2c_read_regs(client, ISL1208_REG_USR1 + off, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return ret == 0 ? count : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static int isl1208_nvmem_write(void *priv, unsigned int off, void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct isl1208_state *isl1208 = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct i2c_client *client = to_i2c_client(isl1208->rtc->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* nvmem sanitizes off/count for us, but count==0 is possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (!count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ret = isl1208_i2c_set_regs(client, ISL1208_REG_USR1 + off, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return ret == 0 ? count : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static const struct nvmem_config isl1208_nvmem_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .name = "isl1208_nvram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .word_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* .size from chip specific config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .reg_read = isl1208_nvmem_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .reg_write = isl1208_nvmem_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static int isl1208_setup_irq(struct i2c_client *client, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) int rc = devm_request_threaded_irq(&client->dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) isl1208_rtc_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) IRQF_SHARED | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) isl1208_driver.driver.name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (!rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) device_init_wakeup(&client->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) enable_irq_wake(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) "Unable to request irq %d, no alarm support\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) isl1208_probe(struct i2c_client *client, const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct isl1208_state *isl1208;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) int evdet_irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (isl1208_i2c_validate_client(client) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* Allocate driver state, point i2c client data to it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) isl1208 = devm_kzalloc(&client->dev, sizeof(*isl1208), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (!isl1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) i2c_set_clientdata(client, isl1208);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* Determine which chip we have */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (client->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) isl1208->config = of_device_get_match_data(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (!isl1208->config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (id->driver_data >= ISL_LAST_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) isl1208->config = &isl1208_configs[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) isl1208->rtc = devm_rtc_allocate_device(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (IS_ERR(isl1208->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return PTR_ERR(isl1208->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) isl1208->rtc->ops = &isl1208_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* Setup nvmem configuration in driver state struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) isl1208->nvmem_config = isl1208_nvmem_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) isl1208->nvmem_config.size = isl1208->config->nvmem_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) isl1208->nvmem_config.priv = isl1208;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) rc = isl1208_i2c_get_sr(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) dev_err(&client->dev, "reading status failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (rc & ISL1208_REG_SR_RTCF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) dev_warn(&client->dev, "rtc power failure detected, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) "please set clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (isl1208->config->has_tamper) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct device_node *np = client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) u32 evienb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) rc = i2c_smbus_read_byte_data(client, ISL1219_REG_EV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) dev_err(&client->dev, "failed to read EV reg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) rc |= ISL1219_REG_EV_EVEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (!of_property_read_u32(np, "isil,ev-evienb", &evienb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (evienb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) rc |= ISL1219_REG_EV_EVIENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) rc &= ~ISL1219_REG_EV_EVIENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) rc = i2c_smbus_write_byte_data(client, ISL1219_REG_EV, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) dev_err(&client->dev, "could not enable tamper detection\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) evdet_irq = of_irq_get_byname(np, "evdet");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (isl1208->config->has_timestamp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) rc = rtc_add_group(isl1208->rtc, &isl1219_rtc_sysfs_files);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) rc = rtc_add_group(isl1208->rtc, &isl1208_rtc_sysfs_files);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (client->irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) rc = isl1208_setup_irq(client, client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (evdet_irq > 0 && evdet_irq != client->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) rc = isl1208_setup_irq(client, evdet_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) rc = rtc_nvmem_register(isl1208->rtc, &isl1208->nvmem_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return rtc_register_device(isl1208->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static struct i2c_driver isl1208_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .name = "rtc-isl1208",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .of_match_table = of_match_ptr(isl1208_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .probe = isl1208_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .id_table = isl1208_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) module_i2c_driver(isl1208_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) MODULE_AUTHOR("Herbert Valerio Riedel <hvr@gnu.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) MODULE_DESCRIPTION("Intersil ISL1208 RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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