^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * An I2C driver for the Intersil ISL 12026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2018 Cavium, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ISL12026_REG_PWR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) # define ISL12026_REG_PWR_BSW BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) # define ISL12026_REG_PWR_SBIB BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ISL12026_REG_SC 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ISL12026_REG_HR 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) # define ISL12026_REG_HR_MIL BIT(7) /* military or 24 hour time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ISL12026_REG_SR 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) # define ISL12026_REG_SR_RTCF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) # define ISL12026_REG_SR_WEL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) # define ISL12026_REG_SR_RWEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) # define ISL12026_REG_SR_MBZ BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) # define ISL12026_REG_SR_OSCF BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* The EEPROM array responds at i2c address 0x57 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ISL12026_EEPROM_ADDR 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ISL12026_PAGESIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ISL12026_NVMEM_WRITE_TIME 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct isl12026 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct i2c_client *nvm_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int isl12026_read_reg(struct i2c_client *client, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u8 addr[] = {0, reg};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct i2c_msg msgs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .len = sizeof(addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .buf = addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .buf = &val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (ret != ARRAY_SIZE(msgs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) dev_err(&client->dev, "read reg error, ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ret = ret < 0 ? ret : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ret = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int isl12026_arm_write(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u8 op[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .buf = op
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Set SR.WEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) op[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) op[1] = ISL12026_REG_SR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) op[2] = ISL12026_REG_SR_WEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) msg.len = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (ret != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) dev_err(&client->dev, "write error SR.WEL, ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ret = ret < 0 ? ret : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Set SR.WEL and SR.RWEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) op[2] = ISL12026_REG_SR_WEL | ISL12026_REG_SR_RWEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) msg.len = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (ret != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "write error SR.WEL|SR.RWEL, ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ret = ret < 0 ? ret : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int isl12026_disarm_write(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u8 op[3] = {0, ISL12026_REG_SR, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .len = sizeof(op),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .buf = op
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (ret != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) "write error SR, ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ret = ret < 0 ? ret : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int isl12026_write_reg(struct i2c_client *client, int reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u8 op[3] = {0, reg, val};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .len = sizeof(op),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .buf = op
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ret = isl12026_arm_write(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (ret != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_err(&client->dev, "write error CCR, ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ret = ret < 0 ? ret : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) msleep(ISL12026_NVMEM_WRITE_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ret = isl12026_disarm_write(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int isl12026_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u8 op[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .len = sizeof(op),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .buf = op
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = isl12026_arm_write(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Set the CCR registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) op[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) op[1] = ISL12026_REG_SC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) op[2] = bin2bcd(tm->tm_sec); /* SC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) op[3] = bin2bcd(tm->tm_min); /* MN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) op[4] = bin2bcd(tm->tm_hour) | ISL12026_REG_HR_MIL; /* HR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) op[5] = bin2bcd(tm->tm_mday); /* DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) op[6] = bin2bcd(tm->tm_mon + 1); /* MO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) op[7] = bin2bcd(tm->tm_year % 100); /* YR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) op[8] = bin2bcd(tm->tm_wday & 7); /* DW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) op[9] = bin2bcd(tm->tm_year >= 100 ? 20 : 19); /* Y2K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (ret != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dev_err(&client->dev, "write error CCR, ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = ret < 0 ? ret : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ret = isl12026_disarm_write(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int isl12026_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u8 ccr[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u8 addr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct i2c_msg msgs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .len = sizeof(addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .buf = addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* First, read SR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) addr[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) addr[1] = ISL12026_REG_SR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) msgs[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) msgs[1].buf = &sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (ret != ARRAY_SIZE(msgs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dev_err(&client->dev, "read error, ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ret = ret < 0 ? ret : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (sr & ISL12026_REG_SR_RTCF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_warn(&client->dev, "Real-Time Clock Failure on read\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (sr & ISL12026_REG_SR_OSCF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_warn(&client->dev, "Oscillator Failure on read\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Second, CCR regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) addr[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) addr[1] = ISL12026_REG_SC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) msgs[1].len = sizeof(ccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) msgs[1].buf = ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (ret != ARRAY_SIZE(msgs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dev_err(&client->dev, "read error, ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ret = ret < 0 ? ret : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) tm->tm_sec = bcd2bin(ccr[0] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) tm->tm_min = bcd2bin(ccr[1] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (ccr[2] & ISL12026_REG_HR_MIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) tm->tm_hour = bcd2bin(ccr[2] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) tm->tm_hour = bcd2bin(ccr[2] & 0x1F) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ((ccr[2] & 0x20) ? 12 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) tm->tm_mday = bcd2bin(ccr[3] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) tm->tm_mon = bcd2bin(ccr[4] & 0x1F) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) tm->tm_year = bcd2bin(ccr[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (bcd2bin(ccr[7]) == 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) tm->tm_year += 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) tm->tm_wday = ccr[6] & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const struct rtc_class_ops isl12026_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .read_time = isl12026_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .set_time = isl12026_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int isl12026_nvm_read(void *p, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) void *val, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct isl12026 *priv = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u8 addr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct i2c_msg msgs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .addr = priv->nvm_client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .len = sizeof(addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .buf = addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .addr = priv->nvm_client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .buf = val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * offset and bytes checked and limited by nvmem core, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * proceed without further checks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ret = mutex_lock_interruptible(&priv->rtc->ops_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* 2 bytes of address, most significant first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) addr[0] = offset >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) addr[1] = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) msgs[1].len = bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ret = i2c_transfer(priv->nvm_client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mutex_unlock(&priv->rtc->ops_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (ret != ARRAY_SIZE(msgs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev_err(&priv->nvm_client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "nvmem read error, ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return ret < 0 ? ret : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int isl12026_nvm_write(void *p, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) void *val, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct isl12026 *priv = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u8 *v = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) size_t chunk_size, num_written;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u8 payload[ISL12026_PAGESIZE + 2]; /* page + 2 address bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct i2c_msg msgs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .addr = priv->nvm_client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .buf = payload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * offset and bytes checked and limited by nvmem core, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * proceed without further checks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ret = mutex_lock_interruptible(&priv->rtc->ops_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) num_written = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) while (bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) chunk_size = round_down(offset, ISL12026_PAGESIZE) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ISL12026_PAGESIZE - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) chunk_size = min(bytes, chunk_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * 2 bytes of address, most significant first, followed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * by page data bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) memcpy(payload + 2, v + num_written, chunk_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) payload[0] = offset >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) payload[1] = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) msgs[0].len = chunk_size + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ret = i2c_transfer(priv->nvm_client->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (ret != ARRAY_SIZE(msgs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dev_err(&priv->nvm_client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) "nvmem write error, ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ret = ret < 0 ? ret : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) bytes -= chunk_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) offset += chunk_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) num_written += chunk_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) msleep(ISL12026_NVMEM_WRITE_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) mutex_unlock(&priv->rtc->ops_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static void isl12026_force_power_modes(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int pwr, requested_pwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u32 bsw_val, sbib_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) bool set_bsw, set_sbib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * If we can read the of_property, set the specified value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * If there is an error reading the of_property (likely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * because it does not exist), keep the current value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ret = of_property_read_u32(client->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) "isil,pwr-bsw", &bsw_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) set_bsw = (ret == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ret = of_property_read_u32(client->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) "isil,pwr-sbib", &sbib_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) set_sbib = (ret == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Check if PWR.BSW and/or PWR.SBIB need specified values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (!set_bsw && !set_sbib)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) pwr = isl12026_read_reg(client, ISL12026_REG_PWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (pwr < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dev_warn(&client->dev, "Error: Failed to read PWR %d\n", pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) requested_pwr = pwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (set_bsw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (bsw_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) requested_pwr |= ISL12026_REG_PWR_BSW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) requested_pwr &= ~ISL12026_REG_PWR_BSW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) } /* else keep current BSW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (set_sbib) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (sbib_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) requested_pwr |= ISL12026_REG_PWR_SBIB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) requested_pwr &= ~ISL12026_REG_PWR_SBIB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) } /* else keep current SBIB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (pwr >= 0 && pwr != requested_pwr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) dev_dbg(&client->dev, "PWR: %02x\n", pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev_dbg(&client->dev, "Updating PWR to: %02x\n", requested_pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) isl12026_write_reg(client, ISL12026_REG_PWR, requested_pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static int isl12026_probe_new(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct isl12026 *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct nvmem_config nvm_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .name = "isl12026-",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .base_dev = &client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .word_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .size = 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .reg_read = isl12026_nvm_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .reg_write = isl12026_nvm_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) i2c_set_clientdata(client, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) isl12026_force_power_modes(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) priv->nvm_client = i2c_new_dummy_device(client->adapter, ISL12026_EEPROM_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (IS_ERR(priv->nvm_client))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return PTR_ERR(priv->nvm_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) priv->rtc = devm_rtc_allocate_device(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ret = PTR_ERR_OR_ZERO(priv->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) priv->rtc->ops = &isl12026_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) nvm_cfg.priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ret = rtc_nvmem_register(priv->rtc, &nvm_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return rtc_register_device(priv->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int isl12026_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct isl12026 *priv = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) i2c_unregister_device(priv->nvm_client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static const struct of_device_id isl12026_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) { .compatible = "isil,isl12026" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) MODULE_DEVICE_TABLE(of, isl12026_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static struct i2c_driver isl12026_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .name = "rtc-isl12026",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .of_match_table = isl12026_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .probe_new = isl12026_probe_new,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .remove = isl12026_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) module_i2c_driver(isl12026_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) MODULE_DESCRIPTION("ISL 12026 RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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