Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Freescale FlexTimer Module (FTM) alarm device driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2014 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright 2019-2020 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/fsl/ftm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/pm_wakeirq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define FTM_SC_CLK(c)		((c) << FTM_SC_CLK_MASK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * Select Fixed frequency clock (32KHz) as clock source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * of FlexTimer Module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define FTM_SC_CLKS_FIXED_FREQ	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define FIXED_FREQ_CLK		32000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* Select 128 (2^7) as divider factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MAX_FREQ_DIV		(1 << FTM_SC_PS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* Maximum counter value in FlexTimer's CNT registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MAX_COUNT_VAL		0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) struct ftm_rtc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct rtc_device *rtc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	bool big_endian;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	u32 alarm_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static inline u32 rtc_readl(struct ftm_rtc *dev, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	if (dev->big_endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		return ioread32be(dev->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		return ioread32(dev->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static inline void rtc_writel(struct ftm_rtc *dev, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	if (dev->big_endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		iowrite32be(val, dev->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		iowrite32(val, dev->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static inline void ftm_counter_enable(struct ftm_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	/* select and enable counter clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	val = rtc_readl(rtc, FTM_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	val |= (FTM_SC_PS_MASK | FTM_SC_CLK(FTM_SC_CLKS_FIXED_FREQ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	rtc_writel(rtc, FTM_SC, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static inline void ftm_counter_disable(struct ftm_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	/* disable counter clock source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	val = rtc_readl(rtc, FTM_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	rtc_writel(rtc, FTM_SC, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static inline void ftm_irq_acknowledge(struct ftm_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	unsigned int timeout = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	 *Fix errata A-007728 for flextimer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	 *	If the FTM counter reaches the FTM_MOD value between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	 *	the reading of the TOF bit and the writing of 0 to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	 *	the TOF bit, the process of clearing the TOF bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 *	does not work as expected when FTMx_CONF[NUMTOF] != 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	 *	and the current TOF count is less than FTMx_CONF[NUMTOF].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	 *	If the above condition is met, the TOF bit remains set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	 *	If the TOF interrupt is enabled (FTMx_SC[TOIE] = 1),the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	 *	TOF interrupt also remains asserted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	 *	Above is the errata discription
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	 *	In one word: software clearing TOF bit not works when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	 *	FTMx_CONF[NUMTOF] was seted as nonzero and FTM counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	 *	reaches the FTM_MOD value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	 *	The workaround is clearing TOF bit until it works
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	 *	(FTM counter doesn't always reache the FTM_MOD anyway),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	 *	which may cost some cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	while ((FTM_SC_TOF & rtc_readl(rtc, FTM_SC)) && timeout--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		rtc_writel(rtc, FTM_SC, rtc_readl(rtc, FTM_SC) & (~FTM_SC_TOF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline void ftm_irq_enable(struct ftm_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	val = rtc_readl(rtc, FTM_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	val |= FTM_SC_TOIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	rtc_writel(rtc, FTM_SC, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static inline void ftm_irq_disable(struct ftm_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	val = rtc_readl(rtc, FTM_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	val &= ~FTM_SC_TOIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	rtc_writel(rtc, FTM_SC, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static inline void ftm_reset_counter(struct ftm_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	 * The CNT register contains the FTM counter value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	 * Reset clears the CNT register. Writing any value to COUNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	 * updates the counter with its initial value, CNTIN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	rtc_writel(rtc, FTM_CNT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void ftm_clean_alarm(struct ftm_rtc *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	ftm_counter_disable(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	rtc_writel(rtc, FTM_CNTIN, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	rtc_writel(rtc, FTM_MOD, ~0U);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	ftm_reset_counter(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static irqreturn_t ftm_rtc_alarm_interrupt(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct ftm_rtc *rtc = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	ftm_irq_acknowledge(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	ftm_irq_disable(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	ftm_clean_alarm(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int ftm_rtc_alarm_irq_enable(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	struct ftm_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		ftm_irq_enable(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		ftm_irq_disable(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)  *	The function is not really getting time from the RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)  *	since FlexTimer is not a RTC device, but we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)  *	get time to setup alarm, so we are using system time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)  *	for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int ftm_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	rtc_time64_to_tm(ktime_get_real_seconds(), tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int ftm_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  * 1. Select fixed frequency clock (32KHz) as clock source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  * 2. Select 128 (2^7) as divider factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  * So clock is 250 Hz (32KHz/128).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  * 3. FlexTimer's CNT register is a 32bit register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  * but the register's 16 bit as counter value,it's other 16 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  * is reserved.So minimum counter value is 0x0,maximum counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  * value is 0xffff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * So max alarm value is 262 (65536 / 250) seconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int ftm_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	time64_t alm_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	unsigned long long cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct ftm_rtc *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	alm_time = rtc_tm_to_time64(&alm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	ftm_clean_alarm(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	cycle = (alm_time - ktime_get_real_seconds()) * rtc->alarm_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (cycle > MAX_COUNT_VAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		pr_err("Out of alarm range {0~262} seconds.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	ftm_irq_disable(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	 * The counter increments until the value of MOD is reached,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	 * at which point the counter is reloaded with the value of CNTIN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	 * The TOF (the overflow flag) bit is set when the FTM counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	 * changes from MOD to CNTIN. So we should using the cycle - 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	rtc_writel(rtc, FTM_MOD, cycle - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	ftm_counter_enable(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	ftm_irq_enable(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const struct rtc_class_ops ftm_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.read_time		= ftm_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.read_alarm		= ftm_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.set_alarm		= ftm_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.alarm_irq_enable	= ftm_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int ftm_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	struct ftm_rtc *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (unlikely(!rtc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		dev_err(&pdev->dev, "cannot alloc memory for rtc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	platform_set_drvdata(pdev, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (IS_ERR(rtc->rtc_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		return PTR_ERR(rtc->rtc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	rtc->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if (IS_ERR(rtc->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		dev_err(&pdev->dev, "cannot ioremap resource for rtc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		return PTR_ERR(rtc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	ret = devm_request_irq(&pdev->dev, irq, ftm_rtc_alarm_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			       0, dev_name(&pdev->dev), rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		dev_err(&pdev->dev, "failed to request irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	rtc->big_endian =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		device_property_read_bool(&pdev->dev, "big-endian");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	rtc->alarm_freq = (u32)FIXED_FREQ_CLK / (u32)MAX_FREQ_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	rtc->rtc_dev->ops = &ftm_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	device_init_wakeup(&pdev->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	ret = dev_pm_set_wake_irq(&pdev->dev, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		dev_err(&pdev->dev, "failed to enable irq wake\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	ret = rtc_register_device(rtc->rtc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		dev_err(&pdev->dev, "can't register rtc device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const struct of_device_id ftm_rtc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	{ .compatible = "fsl,ls1012a-ftm-alarm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	{ .compatible = "fsl,ls1021a-ftm-alarm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	{ .compatible = "fsl,ls1028a-ftm-alarm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	{ .compatible = "fsl,ls1043a-ftm-alarm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	{ .compatible = "fsl,ls1046a-ftm-alarm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	{ .compatible = "fsl,ls1088a-ftm-alarm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	{ .compatible = "fsl,ls208xa-ftm-alarm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	{ .compatible = "fsl,lx2160a-ftm-alarm", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MODULE_DEVICE_TABLE(of, ftm_rtc_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const struct acpi_device_id ftm_imx_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	{"NXP0014",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) MODULE_DEVICE_TABLE(acpi, ftm_imx_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static struct platform_driver ftm_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.probe		= ftm_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		.name	= "ftm-alarm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		.of_match_table = ftm_rtc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		.acpi_match_table = ACPI_PTR(ftm_imx_acpi_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int __init ftm_alarm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	return platform_driver_register(&ftm_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) device_initcall(ftm_alarm_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) MODULE_DESCRIPTION("NXP/Freescale FlexTimer alarm driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MODULE_AUTHOR("Biwen Li <biwen.li@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MODULE_LICENSE("GPL");