^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * rtc-fm3130.c - RTC driver for Ramtron FM3130 I2C chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 Sergey Lapin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on ds1307 driver by James Chapman and David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define FM3130_RTC_CONTROL (0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define FM3130_CAL_CONTROL (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define FM3130_RTC_SECONDS (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define FM3130_RTC_MINUTES (0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define FM3130_RTC_HOURS (0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define FM3130_RTC_DAY (0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define FM3130_RTC_DATE (0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define FM3130_RTC_MONTHS (0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define FM3130_RTC_YEARS (0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FM3130_ALARM_SECONDS (0x9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FM3130_ALARM_MINUTES (0xa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FM3130_ALARM_HOURS (0xb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FM3130_ALARM_DATE (0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define FM3130_ALARM_MONTHS (0xd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define FM3130_ALARM_WP_CONTROL (0xe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FM3130_CAL_CONTROL_BIT_nOSCEN (1 << 7) /* Osciallator enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FM3130_RTC_CONTROL_BIT_LB (1 << 7) /* Low battery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FM3130_RTC_CONTROL_BIT_AF (1 << 6) /* Alarm flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FM3130_RTC_CONTROL_BIT_CF (1 << 5) /* Century overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FM3130_RTC_CONTROL_BIT_POR (1 << 4) /* Power on reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FM3130_RTC_CONTROL_BIT_AEN (1 << 3) /* Alarm enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FM3130_RTC_CONTROL_BIT_CAL (1 << 2) /* Calibration mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FM3130_RTC_CONTROL_BIT_WRITE (1 << 1) /* W=1 -> write mode W=0 normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define FM3130_RTC_CONTROL_BIT_READ (1 << 0) /* R=1 -> read mode R=0 normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FM3130_CLOCK_REGS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FM3130_ALARM_REGS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct fm3130 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u8 reg_addr_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 reg_addr_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u8 regs[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct i2c_msg msg[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int alarm_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int data_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const struct i2c_device_id fm3130_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { "fm3130", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MODULE_DEVICE_TABLE(i2c, fm3130_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define FM3130_MODE_NORMAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define FM3130_MODE_WRITE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define FM3130_MODE_READ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void fm3130_rtc_mode(struct device *dev, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct fm3130 *fm3130 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) fm3130->regs[FM3130_RTC_CONTROL] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) i2c_smbus_read_byte_data(fm3130->client, FM3130_RTC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) case FM3130_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) fm3130->regs[FM3130_RTC_CONTROL] &=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ~(FM3130_RTC_CONTROL_BIT_WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) FM3130_RTC_CONTROL_BIT_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) case FM3130_MODE_WRITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) fm3130->regs[FM3130_RTC_CONTROL] |= FM3130_RTC_CONTROL_BIT_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) case FM3130_MODE_READ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) fm3130->regs[FM3130_RTC_CONTROL] |= FM3130_RTC_CONTROL_BIT_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) dev_dbg(dev, "invalid mode %d\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) i2c_smbus_write_byte_data(fm3130->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) FM3130_RTC_CONTROL, fm3130->regs[FM3130_RTC_CONTROL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int fm3130_get_time(struct device *dev, struct rtc_time *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct fm3130 *fm3130 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (!fm3130->data_valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* We have invalid data in RTC, probably due
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) to battery faults or other problems. Return EIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) for now, it will allow us to set data later instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) of error during probing which disables device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) fm3130_rtc_mode(dev, FM3130_MODE_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* read the RTC date and time registers all at once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) tmp = i2c_transfer(fm3130->client->adapter, fm3130->msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (tmp != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dev_err(dev, "%s error %d\n", "read", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) fm3130_rtc_mode(dev, FM3130_MODE_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dev_dbg(dev, "%s: %15ph\n", "read", fm3130->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) t->tm_sec = bcd2bin(fm3130->regs[FM3130_RTC_SECONDS] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) t->tm_min = bcd2bin(fm3130->regs[FM3130_RTC_MINUTES] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) tmp = fm3130->regs[FM3130_RTC_HOURS] & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) t->tm_hour = bcd2bin(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) t->tm_wday = bcd2bin(fm3130->regs[FM3130_RTC_DAY] & 0x07) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) t->tm_mday = bcd2bin(fm3130->regs[FM3130_RTC_DATE] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) tmp = fm3130->regs[FM3130_RTC_MONTHS] & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) t->tm_mon = bcd2bin(tmp) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* assume 20YY not 19YY, and ignore CF bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) t->tm_year = bcd2bin(fm3130->regs[FM3130_RTC_YEARS]) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dev_dbg(dev, "%s secs=%d, mins=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "read", t->tm_sec, t->tm_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) t->tm_hour, t->tm_mday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) t->tm_mon, t->tm_year, t->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int fm3130_set_time(struct device *dev, struct rtc_time *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct fm3130 *fm3130 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int tmp, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u8 *buf = fm3130->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dev_dbg(dev, "%s secs=%d, mins=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) "write", t->tm_sec, t->tm_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) t->tm_hour, t->tm_mday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) t->tm_mon, t->tm_year, t->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* first register addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) buf[FM3130_RTC_SECONDS] = bin2bcd(t->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) buf[FM3130_RTC_MINUTES] = bin2bcd(t->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) buf[FM3130_RTC_HOURS] = bin2bcd(t->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) buf[FM3130_RTC_DAY] = bin2bcd(t->tm_wday + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) buf[FM3130_RTC_DATE] = bin2bcd(t->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) buf[FM3130_RTC_MONTHS] = bin2bcd(t->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* assume 20YY not 19YY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) tmp = t->tm_year - 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) buf[FM3130_RTC_YEARS] = bin2bcd(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dev_dbg(dev, "%s: %15ph\n", "write", buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) fm3130_rtc_mode(dev, FM3130_MODE_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Writing time registers, we don't support multibyte transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) for (i = 0; i < FM3130_CLOCK_REGS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) i2c_smbus_write_byte_data(fm3130->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) FM3130_RTC_SECONDS + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) fm3130->regs[FM3130_RTC_SECONDS + i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) fm3130_rtc_mode(dev, FM3130_MODE_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* We assume here that data are valid once written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (!fm3130->data_valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) fm3130->data_valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int fm3130_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct fm3130 *fm3130 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct rtc_time *tm = &alrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (!fm3130->alarm_valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * We have invalid alarm in RTC, probably due to battery faults
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * or other problems. Return EIO for now, it will allow us to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * set alarm value later instead of error during probing which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * disables device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* read the RTC alarm registers all at once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) tmp = i2c_transfer(fm3130->client->adapter, &fm3130->msg[2], 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (tmp != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_err(dev, "%s error %d\n", "read", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dev_dbg(dev, "alarm read %02x %02x %02x %02x %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) fm3130->regs[FM3130_ALARM_SECONDS],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) fm3130->regs[FM3130_ALARM_MINUTES],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) fm3130->regs[FM3130_ALARM_HOURS],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) fm3130->regs[FM3130_ALARM_DATE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) fm3130->regs[FM3130_ALARM_MONTHS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) tm->tm_sec = bcd2bin(fm3130->regs[FM3130_ALARM_SECONDS] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) tm->tm_min = bcd2bin(fm3130->regs[FM3130_ALARM_MINUTES] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) tm->tm_hour = bcd2bin(fm3130->regs[FM3130_ALARM_HOURS] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) tm->tm_mday = bcd2bin(fm3130->regs[FM3130_ALARM_DATE] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) tm->tm_mon = bcd2bin(fm3130->regs[FM3130_ALARM_MONTHS] & 0x1F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (tm->tm_mon > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dev_dbg(dev, "%s secs=%d, mins=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "read alarm", tm->tm_sec, tm->tm_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) tm->tm_hour, tm->tm_mday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) tm->tm_mon, tm->tm_year, tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* check if alarm enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) fm3130->regs[FM3130_RTC_CONTROL] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) i2c_smbus_read_byte_data(fm3130->client, FM3130_RTC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if ((fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_AEN) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) (~fm3130->regs[FM3130_RTC_CONTROL] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) FM3130_RTC_CONTROL_BIT_CAL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) alrm->enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int fm3130_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct fm3130 *fm3130 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct rtc_time *tm = &alrm->time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_dbg(dev, "%s secs=%d, mins=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "write alarm", tm->tm_sec, tm->tm_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) tm->tm_hour, tm->tm_mday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) tm->tm_mon, tm->tm_year, tm->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) fm3130->regs[FM3130_ALARM_SECONDS] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) (tm->tm_sec != -1) ? bin2bcd(tm->tm_sec) : 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) fm3130->regs[FM3130_ALARM_MINUTES] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) (tm->tm_min != -1) ? bin2bcd(tm->tm_min) : 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) fm3130->regs[FM3130_ALARM_HOURS] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) (tm->tm_hour != -1) ? bin2bcd(tm->tm_hour) : 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) fm3130->regs[FM3130_ALARM_DATE] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) (tm->tm_mday != -1) ? bin2bcd(tm->tm_mday) : 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) fm3130->regs[FM3130_ALARM_MONTHS] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) (tm->tm_mon != -1) ? bin2bcd(tm->tm_mon + 1) : 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dev_dbg(dev, "alarm write %02x %02x %02x %02x %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) fm3130->regs[FM3130_ALARM_SECONDS],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) fm3130->regs[FM3130_ALARM_MINUTES],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) fm3130->regs[FM3130_ALARM_HOURS],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) fm3130->regs[FM3130_ALARM_DATE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) fm3130->regs[FM3130_ALARM_MONTHS]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Writing time registers, we don't support multibyte transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) for (i = 0; i < FM3130_ALARM_REGS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) i2c_smbus_write_byte_data(fm3130->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) FM3130_ALARM_SECONDS + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) fm3130->regs[FM3130_ALARM_SECONDS + i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) fm3130->regs[FM3130_RTC_CONTROL] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) i2c_smbus_read_byte_data(fm3130->client, FM3130_RTC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* enable or disable alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (alrm->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) i2c_smbus_write_byte_data(fm3130->client, FM3130_RTC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) (fm3130->regs[FM3130_RTC_CONTROL] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ~(FM3130_RTC_CONTROL_BIT_CAL)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) FM3130_RTC_CONTROL_BIT_AEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) i2c_smbus_write_byte_data(fm3130->client, FM3130_RTC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) fm3130->regs[FM3130_RTC_CONTROL] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ~(FM3130_RTC_CONTROL_BIT_CAL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ~(FM3130_RTC_CONTROL_BIT_AEN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* We assume here that data is valid once written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!fm3130->alarm_valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) fm3130->alarm_valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int fm3130_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct fm3130 *fm3130 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) fm3130->regs[FM3130_RTC_CONTROL] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) i2c_smbus_read_byte_data(fm3130->client, FM3130_RTC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev_dbg(dev, "alarm_irq_enable: enable=%d, FM3130_RTC_CONTROL=%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) enabled, fm3130->regs[FM3130_RTC_CONTROL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) switch (enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case 0: /* alarm off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ret = i2c_smbus_write_byte_data(fm3130->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) FM3130_RTC_CONTROL, fm3130->regs[FM3130_RTC_CONTROL] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ~(FM3130_RTC_CONTROL_BIT_CAL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ~(FM3130_RTC_CONTROL_BIT_AEN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case 1: /* alarm on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret = i2c_smbus_write_byte_data(fm3130->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) FM3130_RTC_CONTROL, (fm3130->regs[FM3130_RTC_CONTROL] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ~(FM3130_RTC_CONTROL_BIT_CAL)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) FM3130_RTC_CONTROL_BIT_AEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static const struct rtc_class_ops fm3130_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .read_time = fm3130_get_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .set_time = fm3130_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .read_alarm = fm3130_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .set_alarm = fm3130_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .alarm_irq_enable = fm3130_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static struct i2c_driver fm3130_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int fm3130_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct fm3130 *fm3130;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct i2c_adapter *adapter = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (!i2c_check_functionality(adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) I2C_FUNC_I2C | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) fm3130 = devm_kzalloc(&client->dev, sizeof(struct fm3130), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (!fm3130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) fm3130->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) i2c_set_clientdata(client, fm3130);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) fm3130->reg_addr_time = FM3130_RTC_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) fm3130->reg_addr_alarm = FM3130_ALARM_SECONDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Messages to read time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) fm3130->msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) fm3130->msg[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) fm3130->msg[0].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) fm3130->msg[0].buf = &fm3130->reg_addr_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) fm3130->msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) fm3130->msg[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) fm3130->msg[1].len = FM3130_CLOCK_REGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) fm3130->msg[1].buf = &fm3130->regs[FM3130_RTC_SECONDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* Messages to read alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) fm3130->msg[2].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) fm3130->msg[2].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) fm3130->msg[2].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) fm3130->msg[2].buf = &fm3130->reg_addr_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) fm3130->msg[3].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) fm3130->msg[3].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) fm3130->msg[3].len = FM3130_ALARM_REGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) fm3130->msg[3].buf = &fm3130->regs[FM3130_ALARM_SECONDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) fm3130->alarm_valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) fm3130->data_valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) tmp = i2c_transfer(adapter, fm3130->msg, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (tmp != 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dev_dbg(&client->dev, "read error %d\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) goto exit_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) fm3130->regs[FM3130_RTC_CONTROL] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) i2c_smbus_read_byte_data(client, FM3130_RTC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) fm3130->regs[FM3130_CAL_CONTROL] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) i2c_smbus_read_byte_data(client, FM3130_CAL_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Disabling calibration mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_CAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) i2c_smbus_write_byte_data(client, FM3130_RTC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) fm3130->regs[FM3130_RTC_CONTROL] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ~(FM3130_RTC_CONTROL_BIT_CAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dev_warn(&client->dev, "Disabling calibration mode!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Disabling read and write modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_WRITE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) i2c_smbus_write_byte_data(client, FM3130_RTC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) fm3130->regs[FM3130_RTC_CONTROL] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ~(FM3130_RTC_CONTROL_BIT_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) FM3130_RTC_CONTROL_BIT_WRITE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dev_warn(&client->dev, "Disabling READ or WRITE mode!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* oscillator off? turn it on, so clock can tick. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (fm3130->regs[FM3130_CAL_CONTROL] & FM3130_CAL_CONTROL_BIT_nOSCEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) i2c_smbus_write_byte_data(client, FM3130_CAL_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) fm3130->regs[FM3130_CAL_CONTROL] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ~(FM3130_CAL_CONTROL_BIT_nOSCEN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* low battery? clear flag, and warn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_LB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) i2c_smbus_write_byte_data(client, FM3130_RTC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) fm3130->regs[FM3130_RTC_CONTROL] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ~(FM3130_RTC_CONTROL_BIT_LB));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dev_warn(&client->dev, "Low battery!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* check if Power On Reset bit is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (fm3130->regs[FM3130_RTC_CONTROL] & FM3130_RTC_CONTROL_BIT_POR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) i2c_smbus_write_byte_data(client, FM3130_RTC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) fm3130->regs[FM3130_RTC_CONTROL] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ~FM3130_RTC_CONTROL_BIT_POR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dev_dbg(&client->dev, "POR bit is set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* ACS is controlled by alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) i2c_smbus_write_byte_data(client, FM3130_ALARM_WP_CONTROL, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* alarm registers sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) tmp = bcd2bin(fm3130->regs[FM3130_RTC_SECONDS] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (tmp > 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) goto bad_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) tmp = bcd2bin(fm3130->regs[FM3130_RTC_MINUTES] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (tmp > 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) goto bad_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) tmp = bcd2bin(fm3130->regs[FM3130_RTC_HOURS] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (tmp > 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) goto bad_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) tmp = bcd2bin(fm3130->regs[FM3130_RTC_DATE] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (tmp == 0 || tmp > 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) goto bad_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) tmp = bcd2bin(fm3130->regs[FM3130_RTC_MONTHS] & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (tmp == 0 || tmp > 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) goto bad_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) fm3130->alarm_valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) bad_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* clock registers sanity chek */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) tmp = bcd2bin(fm3130->regs[FM3130_RTC_SECONDS] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (tmp > 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) goto bad_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) tmp = bcd2bin(fm3130->regs[FM3130_RTC_MINUTES] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (tmp > 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) goto bad_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) tmp = bcd2bin(fm3130->regs[FM3130_RTC_HOURS] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (tmp > 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) goto bad_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) tmp = bcd2bin(fm3130->regs[FM3130_RTC_DAY] & 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (tmp == 0 || tmp > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) goto bad_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) tmp = bcd2bin(fm3130->regs[FM3130_RTC_DATE] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (tmp == 0 || tmp > 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) goto bad_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) tmp = bcd2bin(fm3130->regs[FM3130_RTC_MONTHS] & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (tmp == 0 || tmp > 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) goto bad_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) fm3130->data_valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) bad_clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (!fm3130->data_valid || !fm3130->alarm_valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dev_dbg(&client->dev, "%s: %15ph\n", "bogus registers",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) fm3130->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* We won't bail out here because we just got invalid data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) Time setting from u-boot doesn't work anyway */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) fm3130->rtc = devm_rtc_device_register(&client->dev, client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) &fm3130_rtc_ops, THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (IS_ERR(fm3130->rtc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) err = PTR_ERR(fm3130->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) "unable to register the class device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) goto exit_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) exit_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static struct i2c_driver fm3130_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .name = "rtc-fm3130",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .probe = fm3130_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .id_table = fm3130_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) module_i2c_driver(fm3130_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MODULE_DESCRIPTION("RTC driver for FM3130");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) MODULE_AUTHOR("Sergey Lapin <slapin@ossfans.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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