^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * RTC client/driver for the Maxim/Dallas DS3232/DS3234 Real-Time Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009-2011 Freescale Semiconductor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Jack Lan <jack.lan@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2008 MIMOMax Wireless Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DS3232_REG_SECONDS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DS3232_REG_MINUTES 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DS3232_REG_HOURS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DS3232_REG_AMPM 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DS3232_REG_DAY 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DS3232_REG_DATE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DS3232_REG_MONTH 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DS3232_REG_CENTURY 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DS3232_REG_YEAR 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DS3232_REG_ALARM1 0x07 /* Alarm 1 BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DS3232_REG_ALARM2 0x0B /* Alarm 2 BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DS3232_REG_CR 0x0E /* Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) # define DS3232_REG_CR_nEOSC 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) # define DS3232_REG_CR_INTCN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) # define DS3232_REG_CR_A2IE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) # define DS3232_REG_CR_A1IE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DS3232_REG_SR 0x0F /* control/status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) # define DS3232_REG_SR_OSF 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) # define DS3232_REG_SR_BSY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) # define DS3232_REG_SR_A2F 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) # define DS3232_REG_SR_A1F 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DS3232_REG_TEMPERATURE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DS3232_REG_SRAM_START 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DS3232_REG_SRAM_END 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DS3232_REG_SRAM_SIZE 236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct ds3232 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) bool suspended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int ds3232_check_rtc_status(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct ds3232 *ds3232 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int control, stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ret = regmap_read(ds3232->regmap, DS3232_REG_SR, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (stat & DS3232_REG_SR_OSF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "oscillator discontinuity flagged, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "time unreliable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) stat &= ~(DS3232_REG_SR_OSF | DS3232_REG_SR_A1F | DS3232_REG_SR_A2F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ret = regmap_write(ds3232->regmap, DS3232_REG_SR, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* If the alarm is pending, clear it before requesting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * the interrupt, so an interrupt event isn't reported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * before everything is initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ret = regmap_read(ds3232->regmap, DS3232_REG_CR, &control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) control &= ~(DS3232_REG_CR_A1IE | DS3232_REG_CR_A2IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) control |= DS3232_REG_CR_INTCN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return regmap_write(ds3232->regmap, DS3232_REG_CR, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int ds3232_read_time(struct device *dev, struct rtc_time *time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct ds3232 *ds3232 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 buf[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int year, month, day, hour, minute, second;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int week, twelve_hr, am_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int century, add_century = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ret = regmap_bulk_read(ds3232->regmap, DS3232_REG_SECONDS, buf, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) second = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) minute = buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) hour = buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) week = buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) day = buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) month = buf[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) year = buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Extract additional information for AM/PM and century */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) twelve_hr = hour & 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) am_pm = hour & 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) century = month & 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Write to rtc_time structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) time->tm_sec = bcd2bin(second);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) time->tm_min = bcd2bin(minute);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (twelve_hr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Convert to 24 hr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (am_pm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) time->tm_hour = bcd2bin(hour & 0x1F) + 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) time->tm_hour = bcd2bin(hour & 0x1F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) time->tm_hour = bcd2bin(hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Day of the week in linux range is 0~6 while 1~7 in RTC chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) time->tm_wday = bcd2bin(week) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) time->tm_mday = bcd2bin(day);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* linux tm_mon range:0~11, while month range is 1~12 in RTC chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) time->tm_mon = bcd2bin(month & 0x7F) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (century)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) add_century = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) time->tm_year = bcd2bin(year) + add_century;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int ds3232_set_time(struct device *dev, struct rtc_time *time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct ds3232 *ds3232 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u8 buf[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Extract time from rtc_time and load into ds3232*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) buf[0] = bin2bcd(time->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) buf[1] = bin2bcd(time->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) buf[2] = bin2bcd(time->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Day of the week in linux range is 0~6 while 1~7 in RTC chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) buf[3] = bin2bcd(time->tm_wday + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) buf[4] = bin2bcd(time->tm_mday); /* Date */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* linux tm_mon range:0~11, while month range is 1~12 in RTC chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) buf[5] = bin2bcd(time->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (time->tm_year >= 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) buf[5] |= 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) buf[6] = bin2bcd(time->tm_year - 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) buf[6] = bin2bcd(time->tm_year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return regmap_bulk_write(ds3232->regmap, DS3232_REG_SECONDS, buf, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * DS3232 has two alarm, we only use alarm1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * According to linux specification, only support one-shot alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * no periodic alarm mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int ds3232_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct ds3232 *ds3232 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int control, stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u8 buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ret = regmap_read(ds3232->regmap, DS3232_REG_SR, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ret = regmap_read(ds3232->regmap, DS3232_REG_CR, &control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ret = regmap_bulk_read(ds3232->regmap, DS3232_REG_ALARM1, buf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) alarm->time.tm_sec = bcd2bin(buf[0] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) alarm->time.tm_min = bcd2bin(buf[1] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) alarm->time.tm_hour = bcd2bin(buf[2] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) alarm->time.tm_mday = bcd2bin(buf[3] & 0x7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) alarm->enabled = !!(control & DS3232_REG_CR_A1IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) alarm->pending = !!(stat & DS3232_REG_SR_A1F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * linux rtc-module does not support wday alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * and only 24h time mode supported indeed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int ds3232_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct ds3232 *ds3232 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int control, stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u8 buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ds3232->irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) buf[0] = bin2bcd(alarm->time.tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) buf[1] = bin2bcd(alarm->time.tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) buf[2] = bin2bcd(alarm->time.tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) buf[3] = bin2bcd(alarm->time.tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* clear alarm interrupt enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ret = regmap_read(ds3232->regmap, DS3232_REG_CR, &control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) control &= ~(DS3232_REG_CR_A1IE | DS3232_REG_CR_A2IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ret = regmap_write(ds3232->regmap, DS3232_REG_CR, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* clear any pending alarm flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ret = regmap_read(ds3232->regmap, DS3232_REG_SR, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) stat &= ~(DS3232_REG_SR_A1F | DS3232_REG_SR_A2F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ret = regmap_write(ds3232->regmap, DS3232_REG_SR, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = regmap_bulk_write(ds3232->regmap, DS3232_REG_ALARM1, buf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (alarm->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) control |= DS3232_REG_CR_A1IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ret = regmap_write(ds3232->regmap, DS3232_REG_CR, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int ds3232_update_alarm(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct ds3232 *ds3232 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ret = regmap_read(ds3232->regmap, DS3232_REG_CR, &control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* enable alarm1 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) control |= DS3232_REG_CR_A1IE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* disable alarm1 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) control &= ~(DS3232_REG_CR_A1IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ret = regmap_write(ds3232->regmap, DS3232_REG_CR, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * Temperature sensor support for ds3232/ds3234 devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * A user-initiated temperature conversion is not started by this function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * so the temperature is updated once every 64 seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int ds3232_hwmon_read_temp(struct device *dev, long int *mC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct ds3232 *ds3232 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u8 temp_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) s16 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ret = regmap_bulk_read(ds3232->regmap, DS3232_REG_TEMPERATURE, temp_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) sizeof(temp_buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * Temperature is represented as a 10-bit code with a resolution of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * 0.25 degree celsius and encoded in two's complement format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) temp = (temp_buf[0] << 8) | temp_buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) temp >>= 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) *mC = temp * 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static umode_t ds3232_hwmon_is_visible(const void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (type != hwmon_temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int ds3232_hwmon_read(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 attr, int channel, long *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) err = ds3232_hwmon_read_temp(dev, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) err = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static u32 ds3232_hwmon_chip_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) HWMON_C_REGISTER_TZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const struct hwmon_channel_info ds3232_hwmon_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .type = hwmon_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .config = ds3232_hwmon_chip_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static u32 ds3232_hwmon_temp_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) HWMON_T_INPUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static const struct hwmon_channel_info ds3232_hwmon_temp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .type = hwmon_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .config = ds3232_hwmon_temp_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static const struct hwmon_channel_info *ds3232_hwmon_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) &ds3232_hwmon_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) &ds3232_hwmon_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const struct hwmon_ops ds3232_hwmon_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .is_visible = ds3232_hwmon_is_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .read = ds3232_hwmon_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const struct hwmon_chip_info ds3232_hwmon_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .ops = &ds3232_hwmon_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .info = ds3232_hwmon_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static void ds3232_hwmon_register(struct device *dev, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct ds3232 *ds3232 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct device *hwmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (!IS_ENABLED(CONFIG_RTC_DRV_DS3232_HWMON))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) hwmon_dev = devm_hwmon_device_register_with_info(dev, name, ds3232,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) &ds3232_hwmon_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (IS_ERR(hwmon_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_err(dev, "unable to register hwmon device %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) PTR_ERR(hwmon_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int ds3232_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct ds3232 *ds3232 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (ds3232->irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return ds3232_update_alarm(dev, enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static irqreturn_t ds3232_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct device *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct ds3232 *ds3232 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct mutex *lock = &ds3232->rtc->ops_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int stat, control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) mutex_lock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ret = regmap_read(ds3232->regmap, DS3232_REG_SR, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (stat & DS3232_REG_SR_A1F) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ret = regmap_read(ds3232->regmap, DS3232_REG_CR, &control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dev_warn(ds3232->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) "Read Control Register error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* disable alarm1 interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) control &= ~(DS3232_REG_CR_A1IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ret = regmap_write(ds3232->regmap, DS3232_REG_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev_warn(ds3232->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) "Write Control Register error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* clear the alarm pend flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) stat &= ~DS3232_REG_SR_A1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ret = regmap_write(ds3232->regmap, DS3232_REG_SR, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev_warn(ds3232->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) "Write Status Register error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) rtc_update_irq(ds3232->rtc, 1, RTC_AF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) mutex_unlock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static const struct rtc_class_ops ds3232_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .read_time = ds3232_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .set_time = ds3232_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .read_alarm = ds3232_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .set_alarm = ds3232_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .alarm_irq_enable = ds3232_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int ds3232_nvmem_read(void *priv, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct regmap *ds3232_regmap = (struct regmap *)priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return regmap_bulk_read(ds3232_regmap, DS3232_REG_SRAM_START + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) val, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static int ds3232_nvmem_write(void *priv, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct regmap *ds3232_regmap = (struct regmap *)priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return regmap_bulk_write(ds3232_regmap, DS3232_REG_SRAM_START + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) val, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int ds3232_probe(struct device *dev, struct regmap *regmap, int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct ds3232 *ds3232;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct nvmem_config nvmem_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .name = "ds3232_sram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .size = DS3232_REG_SRAM_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .word_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .reg_read = ds3232_nvmem_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .reg_write = ds3232_nvmem_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .priv = regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .type = NVMEM_TYPE_BATTERY_BACKED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ds3232 = devm_kzalloc(dev, sizeof(*ds3232), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (!ds3232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ds3232->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ds3232->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ds3232->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dev_set_drvdata(dev, ds3232);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ret = ds3232_check_rtc_status(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (ds3232->irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) device_init_wakeup(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ds3232_hwmon_register(dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ds3232->rtc = devm_rtc_device_register(dev, name, &ds3232_rtc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (IS_ERR(ds3232->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return PTR_ERR(ds3232->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = rtc_nvmem_register(ds3232->rtc, &nvmem_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if(ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (ds3232->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ret = devm_request_threaded_irq(dev, ds3232->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ds3232_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) IRQF_SHARED | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) device_set_wakeup_capable(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ds3232->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dev_err(dev, "unable to request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int ds3232_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct ds3232 *ds3232 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (device_may_wakeup(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (enable_irq_wake(ds3232->irq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) dev_warn_once(dev, "Cannot set wakeup source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int ds3232_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct ds3232 *ds3232 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) disable_irq_wake(ds3232->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static const struct dev_pm_ops ds3232_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) SET_SYSTEM_SLEEP_PM_OPS(ds3232_suspend, ds3232_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #if IS_ENABLED(CONFIG_I2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static int ds3232_i2c_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static const struct regmap_config config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .max_register = DS3232_REG_SRAM_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) regmap = devm_regmap_init_i2c(client, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) dev_err(&client->dev, "%s: regmap allocation failed: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) __func__, PTR_ERR(regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return ds3232_probe(&client->dev, regmap, client->irq, client->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static const struct i2c_device_id ds3232_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) { "ds3232", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) MODULE_DEVICE_TABLE(i2c, ds3232_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static const struct of_device_id ds3232_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) { .compatible = "dallas,ds3232" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) MODULE_DEVICE_TABLE(of, ds3232_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static struct i2c_driver ds3232_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .name = "rtc-ds3232",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .of_match_table = of_match_ptr(ds3232_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .pm = &ds3232_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .probe = ds3232_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .id_table = ds3232_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static int ds3232_register_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return i2c_add_driver(&ds3232_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static void ds3232_unregister_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) i2c_del_driver(&ds3232_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static int ds3232_register_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static void ds3232_unregister_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #if IS_ENABLED(CONFIG_SPI_MASTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int ds3234_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static const struct regmap_config config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .max_register = DS3232_REG_SRAM_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .write_flag_mask = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) regmap = devm_regmap_init_spi(spi, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) __func__, PTR_ERR(regmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) spi->mode = SPI_MODE_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) spi->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) spi_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) res = regmap_read(regmap, DS3232_REG_SECONDS, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /* Control settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * CONTROL_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * BIT 7 6 5 4 3 2 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * EOSC BBSQW CONV RS2 RS1 INTCN A2IE A1IE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * 0 0 0 1 1 1 0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * CONTROL_STAT_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * BIT 7 6 5 4 3 2 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * OSF BB32kHz CRATE1 CRATE0 EN32kHz BSY A2F A1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * 1 0 0 0 1 0 0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) res = regmap_read(regmap, DS3232_REG_CR, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) res = regmap_write(regmap, DS3232_REG_CR, tmp & 0x1c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) res = regmap_read(regmap, DS3232_REG_SR, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) res = regmap_write(regmap, DS3232_REG_SR, tmp & 0x88);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* Print our settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) res = regmap_read(regmap, DS3232_REG_CR, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dev_info(&spi->dev, "Control Reg: 0x%02x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) res = regmap_read(regmap, DS3232_REG_SR, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dev_info(&spi->dev, "Ctrl/Stat Reg: 0x%02x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return ds3232_probe(&spi->dev, regmap, spi->irq, "ds3234");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static struct spi_driver ds3234_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .name = "ds3234",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .probe = ds3234_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static int ds3234_register_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return spi_register_driver(&ds3234_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static void ds3234_unregister_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) spi_unregister_driver(&ds3234_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static int ds3234_register_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static void ds3234_unregister_driver(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static int __init ds323x_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ret = ds3232_register_driver();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) pr_err("Failed to register ds3232 driver: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) ret = ds3234_register_driver();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) pr_err("Failed to register ds3234 driver: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ds3232_unregister_driver();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) module_init(ds323x_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static void __exit ds323x_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ds3234_unregister_driver();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ds3232_unregister_driver();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) module_exit(ds323x_exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) MODULE_AUTHOR("Srikanth Srinivasan <srikanth.srinivasan@freescale.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) MODULE_AUTHOR("Dennis Aberilla <denzzzhome@yahoo.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) MODULE_DESCRIPTION("Maxim/Dallas DS3232/DS3234 RTC Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) MODULE_ALIAS("spi:ds3234");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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