^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (C) 2012 Sven Schnelle <svens@stackframe.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_data/rtc-ds2404.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DS2404_STATUS_REG 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DS2404_CONTROL_REG 0x201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DS2404_RTC_REG 0x202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DS2404_WRITE_SCRATCHPAD_CMD 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DS2404_READ_SCRATCHPAD_CMD 0xaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DS2404_COPY_SCRATCHPAD_CMD 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DS2404_READ_MEMORY_CMD 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DS2404_RST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DS2404_CLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DS2404_DQ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct ds2404_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned int gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct ds2404 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct ds2404_gpio *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct ds2404_gpio ds2404_gpio[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { "RTC RST", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { "RTC CLK", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { "RTC DQ", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int ds2404_gpio_map(struct ds2404 *chip, struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct ds2404_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ds2404_gpio[DS2404_RST].gpio = pdata->gpio_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ds2404_gpio[DS2404_CLK].gpio = pdata->gpio_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ds2404_gpio[DS2404_DQ].gpio = pdata->gpio_dq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) for (i = 0; i < ARRAY_SIZE(ds2404_gpio); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) err = gpio_request(ds2404_gpio[i].gpio, ds2404_gpio[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) dev_err(&pdev->dev, "error mapping gpio %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ds2404_gpio[i].name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) goto err_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (i != DS2404_DQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) gpio_direction_output(ds2404_gpio[i].gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) chip->gpio = ds2404_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) err_request:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) while (--i >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) gpio_free(ds2404_gpio[i].gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static void ds2404_gpio_unmap(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) for (i = 0; i < ARRAY_SIZE(ds2404_gpio); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) gpio_free(ds2404_gpio[i].gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void ds2404_reset(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) gpio_set_value(ds2404_gpio[DS2404_RST].gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) udelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) gpio_set_value(ds2404_gpio[DS2404_RST].gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) gpio_set_value(ds2404_gpio[DS2404_CLK].gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) gpio_direction_output(ds2404_gpio[DS2404_DQ].gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void ds2404_write_byte(struct device *dev, u8 byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) gpio_direction_output(ds2404_gpio[DS2404_DQ].gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) gpio_set_value(ds2404_gpio[DS2404_DQ].gpio, byte & (1 << i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) gpio_set_value(ds2404_gpio[DS2404_CLK].gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) gpio_set_value(ds2404_gpio[DS2404_CLK].gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static u8 ds2404_read_byte(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) gpio_direction_input(ds2404_gpio[DS2404_DQ].gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) gpio_set_value(ds2404_gpio[DS2404_CLK].gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (gpio_get_value(ds2404_gpio[DS2404_DQ].gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ret |= 1 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) gpio_set_value(ds2404_gpio[DS2404_CLK].gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void ds2404_read_memory(struct device *dev, u16 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int length, u8 *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ds2404_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ds2404_write_byte(dev, DS2404_READ_MEMORY_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ds2404_write_byte(dev, offset & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ds2404_write_byte(dev, (offset >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) while (length--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *out++ = ds2404_read_byte(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void ds2404_write_memory(struct device *dev, u16 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int length, u8 *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u8 ta01, ta02, es;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ds2404_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ds2404_write_byte(dev, DS2404_WRITE_SCRATCHPAD_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ds2404_write_byte(dev, offset & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ds2404_write_byte(dev, (offset >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) for (i = 0; i < length; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ds2404_write_byte(dev, out[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ds2404_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ds2404_write_byte(dev, DS2404_READ_SCRATCHPAD_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ta01 = ds2404_read_byte(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ta02 = ds2404_read_byte(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) es = ds2404_read_byte(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) for (i = 0; i < length; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (out[i] != ds2404_read_byte(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dev_err(dev, "read invalid data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ds2404_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ds2404_write_byte(dev, DS2404_COPY_SCRATCHPAD_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ds2404_write_byte(dev, ta01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ds2404_write_byte(dev, ta02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ds2404_write_byte(dev, es);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) gpio_direction_input(ds2404_gpio[DS2404_DQ].gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) while (gpio_get_value(ds2404_gpio[DS2404_DQ].gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static void ds2404_enable_osc(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u8 in[1] = { 0x10 }; /* enable oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ds2404_write_memory(dev, 0x201, 1, in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int ds2404_read_time(struct device *dev, struct rtc_time *dt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned long time = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) __le32 hw_time = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ds2404_read_memory(dev, 0x203, 4, (u8 *)&hw_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) time = le32_to_cpu(hw_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) rtc_time64_to_tm(time, dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int ds2404_set_time(struct device *dev, struct rtc_time *dt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 time = cpu_to_le32(rtc_tm_to_time64(dt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ds2404_write_memory(dev, 0x203, 4, (u8 *)&time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const struct rtc_class_ops ds2404_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .read_time = ds2404_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .set_time = ds2404_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct ds2404_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct ds2404 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int retval = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) chip = devm_kzalloc(&pdev->dev, sizeof(struct ds2404), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) chip->rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (IS_ERR(chip->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return PTR_ERR(chip->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) retval = ds2404_gpio_map(chip, pdev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) retval = devm_add_action_or_reset(&pdev->dev, ds2404_gpio_unmap, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev_info(&pdev->dev, "using GPIOs RST:%d, CLK:%d, DQ:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) chip->gpio[DS2404_RST].gpio, chip->gpio[DS2404_CLK].gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) chip->gpio[DS2404_DQ].gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) platform_set_drvdata(pdev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) chip->rtc->ops = &ds2404_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) chip->rtc->range_max = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) retval = rtc_register_device(chip->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ds2404_enable_osc(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static struct platform_driver rtc_device_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .probe = rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .name = "ds2404",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) module_platform_driver(rtc_device_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MODULE_DESCRIPTION("DS2404 RTC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MODULE_AUTHOR("Sven Schnelle");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MODULE_ALIAS("platform:ds2404");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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