Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * An rtc driver for the Dallas DS1742
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2006 Atsushi Nemoto <anemo@mba.ocn.ne.jp>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2006 Torsten Ertbjerg Rasmussen <tr@newtec.dk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  - nvram size determined from resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  - this ds1742 driver now supports ds1743.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define RTC_SIZE		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define RTC_CONTROL		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define RTC_CENTURY		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define RTC_SECONDS		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define RTC_MINUTES		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define RTC_HOURS		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define RTC_DAY			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define RTC_DATE		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define RTC_MONTH		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define RTC_YEAR		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define RTC_CENTURY_MASK	0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define RTC_SECONDS_MASK	0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define RTC_DAY_MASK		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* Bits in the Control/Century register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define RTC_WRITE		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define RTC_READ		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /* Bits in the Seconds register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define RTC_STOP		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /* Bits in the Day register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define RTC_BATT_FLAG		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) struct rtc_plat_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	void __iomem *ioaddr_nvram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	void __iomem *ioaddr_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	unsigned long last_jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static int ds1742_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	void __iomem *ioaddr = pdata->ioaddr_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u8 century;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	century = bin2bcd((tm->tm_year + 1900) / 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	writeb(RTC_WRITE, ioaddr + RTC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	writeb(bin2bcd(tm->tm_year % 100), ioaddr + RTC_YEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	writeb(bin2bcd(tm->tm_mon + 1), ioaddr + RTC_MONTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	writeb(bin2bcd(tm->tm_wday) & RTC_DAY_MASK, ioaddr + RTC_DAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	writeb(bin2bcd(tm->tm_mday), ioaddr + RTC_DATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	writeb(bin2bcd(tm->tm_hour), ioaddr + RTC_HOURS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	writeb(bin2bcd(tm->tm_min), ioaddr + RTC_MINUTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	writeb(bin2bcd(tm->tm_sec) & RTC_SECONDS_MASK, ioaddr + RTC_SECONDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	/* RTC_CENTURY and RTC_CONTROL share same register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	writeb(RTC_WRITE | (century & RTC_CENTURY_MASK), ioaddr + RTC_CENTURY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	writeb(century & RTC_CENTURY_MASK, ioaddr + RTC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static int ds1742_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct rtc_plat_data *pdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	void __iomem *ioaddr = pdata->ioaddr_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	unsigned int year, month, day, hour, minute, second, week;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	unsigned int century;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	/* give enough time to update RTC in case of continuous read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (pdata->last_jiffies == jiffies)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	pdata->last_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	writeb(RTC_READ, ioaddr + RTC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	second = readb(ioaddr + RTC_SECONDS) & RTC_SECONDS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	minute = readb(ioaddr + RTC_MINUTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	hour = readb(ioaddr + RTC_HOURS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	day = readb(ioaddr + RTC_DATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	week = readb(ioaddr + RTC_DAY) & RTC_DAY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	month = readb(ioaddr + RTC_MONTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	year = readb(ioaddr + RTC_YEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	century = readb(ioaddr + RTC_CENTURY) & RTC_CENTURY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	writeb(0, ioaddr + RTC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	tm->tm_sec = bcd2bin(second);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	tm->tm_min = bcd2bin(minute);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	tm->tm_hour = bcd2bin(hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	tm->tm_mday = bcd2bin(day);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	tm->tm_wday = bcd2bin(week);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	tm->tm_mon = bcd2bin(month) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	/* year is 1900 + tm->tm_year */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	tm->tm_year = bcd2bin(year) + bcd2bin(century) * 100 - 1900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const struct rtc_class_ops ds1742_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.read_time	= ds1742_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.set_time	= ds1742_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int ds1742_nvram_read(void *priv, unsigned int pos, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			     size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct rtc_plat_data *pdata = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	void __iomem *ioaddr = pdata->ioaddr_nvram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	u8 *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	for (; bytes; bytes--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		*buf++ = readb(ioaddr + pos++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int ds1742_nvram_write(void *priv, unsigned int pos, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			      size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	struct rtc_plat_data *pdata = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	void __iomem *ioaddr = pdata->ioaddr_nvram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	u8 *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	for (; bytes; bytes--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		writeb(*buf++, ioaddr + pos++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int ds1742_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	unsigned int cen, sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	struct rtc_plat_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct nvmem_config nvmem_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		.name = "ds1742_nvram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		.reg_read = ds1742_nvram_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		.reg_write = ds1742_nvram_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	ioaddr = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (IS_ERR(ioaddr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		return PTR_ERR(ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	pdata->ioaddr_nvram = ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	pdata->ioaddr_rtc = ioaddr + resource_size(res) - RTC_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	nvmem_cfg.size = resource_size(res) - RTC_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	nvmem_cfg.priv = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	/* turn RTC on if it was not on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	ioaddr = pdata->ioaddr_rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	sec = readb(ioaddr + RTC_SECONDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (sec & RTC_STOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		sec &= RTC_SECONDS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		cen = readb(ioaddr + RTC_CENTURY) & RTC_CENTURY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		writeb(RTC_WRITE, ioaddr + RTC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		writeb(sec, ioaddr + RTC_SECONDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		writeb(cen & RTC_CENTURY_MASK, ioaddr + RTC_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (!(readb(ioaddr + RTC_DAY) & RTC_BATT_FLAG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		dev_warn(&pdev->dev, "voltage-low detected.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	pdata->last_jiffies = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	platform_set_drvdata(pdev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	rtc = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (IS_ERR(rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		return PTR_ERR(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	rtc->ops = &ds1742_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	rtc->nvram_old_abi = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	ret = rtc_register_device(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (rtc_nvmem_register(rtc, &nvmem_cfg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		dev_err(&pdev->dev, "Unable to register nvmem\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const struct of_device_id __maybe_unused ds1742_rtc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	{ .compatible = "maxim,ds1742", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MODULE_DEVICE_TABLE(of, ds1742_rtc_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct platform_driver ds1742_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.probe		= ds1742_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		.name	= "rtc-ds1742",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		.of_match_table = of_match_ptr(ds1742_rtc_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) module_platform_driver(ds1742_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MODULE_DESCRIPTION("Dallas DS1742 RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MODULE_ALIAS("platform:rtc-ds1742");