^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * An rtc driver for the Dallas/Maxim DS1685/DS1687 and related real-time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * References:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Application Note 90, Using the Multiplex Bus RTC Extended Features.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/rtc/ds1685.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/proc_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Standard read/write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * all registers are mapped in CPU address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * ds1685_read - read a value from an rtc register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @rtc: pointer to the ds1685 rtc structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @reg: the register address to read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ds1685_read(struct ds1685_priv *rtc, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return readb((u8 __iomem *)rtc->regs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) (reg * rtc->regstep));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * ds1685_write - write a value to an rtc register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @rtc: pointer to the ds1685 rtc structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @reg: the register address to write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @value: value to write to the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ds1685_write(struct ds1685_priv *rtc, int reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) writeb(value, ((u8 __iomem *)rtc->regs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) (reg * rtc->regstep)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * Indirect read/write functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * access happens via address and data register mapped in CPU address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * ds1685_indirect_read - read a value from an rtc register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @rtc: pointer to the ds1685 rtc structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @reg: the register address to read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ds1685_indirect_read(struct ds1685_priv *rtc, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) writeb(reg, rtc->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return readb(rtc->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * ds1685_indirect_write - write a value to an rtc register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @rtc: pointer to the ds1685 rtc structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @reg: the register address to write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @value: value to write to the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ds1685_indirect_write(struct ds1685_priv *rtc, int reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) writeb(reg, rtc->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) writeb(value, rtc->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Inlined functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * ds1685_rtc_bcd2bin - bcd2bin wrapper in case platform doesn't support BCD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @rtc: pointer to the ds1685 rtc structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @val: u8 time value to consider converting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @bcd_mask: u8 mask value if BCD mode is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @bin_mask: u8 mask value if BIN mode is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Returns the value, converted to BIN if originally in BCD and bcd_mode TRUE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static inline u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ds1685_rtc_bcd2bin(struct ds1685_priv *rtc, u8 val, u8 bcd_mask, u8 bin_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (rtc->bcd_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return (bcd2bin(val) & bcd_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return (val & bin_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * ds1685_rtc_bin2bcd - bin2bcd wrapper in case platform doesn't support BCD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @rtc: pointer to the ds1685 rtc structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @val: u8 time value to consider converting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @bin_mask: u8 mask value if BIN mode is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @bcd_mask: u8 mask value if BCD mode is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * Returns the value, converted to BCD if originally in BIN and bcd_mode TRUE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline u8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ds1685_rtc_bin2bcd(struct ds1685_priv *rtc, u8 val, u8 bin_mask, u8 bcd_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (rtc->bcd_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return (bin2bcd(val) & bcd_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return (val & bin_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * s1685_rtc_check_mday - check validity of the day of month.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * @rtc: pointer to the ds1685 rtc structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @mday: day of month.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * Returns -EDOM if the day of month is not within 1..31 range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ds1685_rtc_check_mday(struct ds1685_priv *rtc, u8 mday)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (rtc->bcd_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (mday < 0x01 || mday > 0x31 || (mday & 0x0f) > 0x09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return -EDOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (mday < 1 || mday > 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return -EDOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * ds1685_rtc_switch_to_bank0 - switch the rtc to bank 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @rtc: pointer to the ds1685 rtc structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ds1685_rtc_switch_to_bank0(struct ds1685_priv *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) rtc->write(rtc, RTC_CTRL_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) (rtc->read(rtc, RTC_CTRL_A) & ~(RTC_CTRL_A_DV0)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * ds1685_rtc_switch_to_bank1 - switch the rtc to bank 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @rtc: pointer to the ds1685 rtc structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ds1685_rtc_switch_to_bank1(struct ds1685_priv *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) rtc->write(rtc, RTC_CTRL_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) (rtc->read(rtc, RTC_CTRL_A) | RTC_CTRL_A_DV0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * ds1685_rtc_begin_data_access - prepare the rtc for data access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @rtc: pointer to the ds1685 rtc structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * This takes several steps to prepare the rtc for access to get/set time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * and alarm values from the rtc registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * - Sets the SET bit in Control Register B.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * - Reads Ext Control Register 4A and checks the INCR bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * - If INCR is active, a short delay is added before Ext Control Register 4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * is read again in a loop until INCR is inactive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * - Switches the rtc to bank 1. This allows access to all relevant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * data for normal rtc operation, as bank 0 contains only the nvram.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ds1685_rtc_begin_data_access(struct ds1685_priv *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Set the SET bit in Ctrl B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) rtc->write(rtc, RTC_CTRL_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Switch to Bank 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ds1685_rtc_switch_to_bank1(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * ds1685_rtc_end_data_access - end data access on the rtc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * @rtc: pointer to the ds1685 rtc structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * This ends what was started by ds1685_rtc_begin_data_access:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * - Switches the rtc back to bank 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * - Clears the SET bit in Control Register B.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ds1685_rtc_end_data_access(struct ds1685_priv *rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Switch back to Bank 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ds1685_rtc_switch_to_bank0(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Clear the SET bit in Ctrl B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) rtc->write(rtc, RTC_CTRL_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * ds1685_rtc_get_ssn - retrieve the silicon serial number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @rtc: pointer to the ds1685 rtc structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * @ssn: u8 array to hold the bits of the silicon serial number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * This number starts at 0x40, and is 8-bytes long, ending at 0x47. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * first byte is the model number, the next six bytes are the serial number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * digits, and the final byte is a CRC check byte. Together, they form the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * silicon serial number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * These values are stored in bank1, so ds1685_rtc_switch_to_bank1 must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * called first before calling this function, else data will be read out of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * the bank0 NVRAM. Be sure to call ds1685_rtc_switch_to_bank0 when done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ds1685_rtc_get_ssn(struct ds1685_priv *rtc, u8 *ssn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ssn[0] = rtc->read(rtc, RTC_BANK1_SSN_MODEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ssn[1] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ssn[2] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ssn[3] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ssn[4] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ssn[5] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ssn[6] = rtc->read(rtc, RTC_BANK1_SSN_BYTE_6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ssn[7] = rtc->read(rtc, RTC_BANK1_SSN_CRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Read/Set Time & Alarm functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * ds1685_rtc_read_time - reads the time registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * @dev: pointer to device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * @tm: pointer to rtc_time structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ds1685_rtc_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct ds1685_priv *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u8 century;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u8 seconds, minutes, hours, wday, mday, month, years;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Fetch the time info from the RTC registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ds1685_rtc_begin_data_access(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) seconds = rtc->read(rtc, RTC_SECS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) minutes = rtc->read(rtc, RTC_MINS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) hours = rtc->read(rtc, RTC_HRS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) wday = rtc->read(rtc, RTC_WDAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) mday = rtc->read(rtc, RTC_MDAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) month = rtc->read(rtc, RTC_MONTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) years = rtc->read(rtc, RTC_YEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) century = rtc->read(rtc, RTC_CENTURY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ds1685_rtc_end_data_access(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* bcd2bin if needed, perform fixups, and store to rtc_time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) years = ds1685_rtc_bcd2bin(rtc, years, RTC_YEAR_BCD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) RTC_YEAR_BIN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) century = ds1685_rtc_bcd2bin(rtc, century, RTC_CENTURY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) RTC_CENTURY_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) tm->tm_sec = ds1685_rtc_bcd2bin(rtc, seconds, RTC_SECS_BCD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) RTC_SECS_BIN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) tm->tm_min = ds1685_rtc_bcd2bin(rtc, minutes, RTC_MINS_BCD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) RTC_MINS_BIN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) tm->tm_hour = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_24_BCD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) RTC_HRS_24_BIN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) tm->tm_wday = (ds1685_rtc_bcd2bin(rtc, wday, RTC_WDAY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) RTC_WDAY_MASK) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) tm->tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) RTC_MDAY_BIN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) tm->tm_mon = (ds1685_rtc_bcd2bin(rtc, month, RTC_MONTH_BCD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) RTC_MONTH_BIN_MASK) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) tm->tm_year = ((years + (century * 100)) - 1900);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) tm->tm_isdst = 0; /* RTC has hardcoded timezone, so don't use. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * ds1685_rtc_set_time - sets the time registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * @dev: pointer to device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * @tm: pointer to rtc_time structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ds1685_rtc_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct ds1685_priv *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u8 ctrlb, seconds, minutes, hours, wday, mday, month, years, century;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Fetch the time info from rtc_time. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) seconds = ds1685_rtc_bin2bcd(rtc, tm->tm_sec, RTC_SECS_BIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) RTC_SECS_BCD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) minutes = ds1685_rtc_bin2bcd(rtc, tm->tm_min, RTC_MINS_BIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) RTC_MINS_BCD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) hours = ds1685_rtc_bin2bcd(rtc, tm->tm_hour, RTC_HRS_24_BIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) RTC_HRS_24_BCD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) wday = ds1685_rtc_bin2bcd(rtc, (tm->tm_wday + 1), RTC_WDAY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) RTC_WDAY_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) mday = ds1685_rtc_bin2bcd(rtc, tm->tm_mday, RTC_MDAY_BIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) RTC_MDAY_BCD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) month = ds1685_rtc_bin2bcd(rtc, (tm->tm_mon + 1), RTC_MONTH_BIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) RTC_MONTH_BCD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) years = ds1685_rtc_bin2bcd(rtc, (tm->tm_year % 100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) RTC_YEAR_BIN_MASK, RTC_YEAR_BCD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) century = ds1685_rtc_bin2bcd(rtc, ((tm->tm_year + 1900) / 100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) RTC_CENTURY_MASK, RTC_CENTURY_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * Perform Sanity Checks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * - Months: !> 12, Month Day != 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * - Month Day !> Max days in current month.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * - Hours !>= 24, Mins !>= 60, Secs !>= 60, & Weekday !> 7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if ((tm->tm_mon > 11) || (mday == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return -EDOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (tm->tm_mday > rtc_month_days(tm->tm_mon, tm->tm_year))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return -EDOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if ((tm->tm_hour >= 24) || (tm->tm_min >= 60) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) (tm->tm_sec >= 60) || (wday > 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return -EDOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * Set the data mode to use and store the time values in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * RTC registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ds1685_rtc_begin_data_access(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ctrlb = rtc->read(rtc, RTC_CTRL_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (rtc->bcd_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ctrlb &= ~(RTC_CTRL_B_DM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ctrlb |= RTC_CTRL_B_DM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) rtc->write(rtc, RTC_CTRL_B, ctrlb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) rtc->write(rtc, RTC_SECS, seconds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) rtc->write(rtc, RTC_MINS, minutes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) rtc->write(rtc, RTC_HRS, hours);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) rtc->write(rtc, RTC_WDAY, wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) rtc->write(rtc, RTC_MDAY, mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) rtc->write(rtc, RTC_MONTH, month);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) rtc->write(rtc, RTC_YEAR, years);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) rtc->write(rtc, RTC_CENTURY, century);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ds1685_rtc_end_data_access(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * ds1685_rtc_read_alarm - reads the alarm registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * @dev: pointer to device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * @alrm: pointer to rtc_wkalrm structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * There are three primary alarm registers: seconds, minutes, and hours.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * A fourth alarm register for the month date is also available in bank1 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * kickstart/wakeup features. The DS1685/DS1687 manual states that a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * "don't care" value ranging from 0xc0 to 0xff may be written into one or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * more of the three alarm bytes to act as a wildcard value. The fourth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * byte doesn't support a "don't care" value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct ds1685_priv *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u8 seconds, minutes, hours, mday, ctrlb, ctrlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Fetch the alarm info from the RTC alarm registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ds1685_rtc_begin_data_access(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) seconds = rtc->read(rtc, RTC_SECS_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) minutes = rtc->read(rtc, RTC_MINS_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) hours = rtc->read(rtc, RTC_HRS_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) mday = rtc->read(rtc, RTC_MDAY_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ctrlb = rtc->read(rtc, RTC_CTRL_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ctrlc = rtc->read(rtc, RTC_CTRL_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ds1685_rtc_end_data_access(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Check the month date for validity. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret = ds1685_rtc_check_mday(rtc, mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * Check the three alarm bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * The Linux RTC system doesn't support the "don't care" capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * of this RTC chip. We check for it anyways in case support is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * added in the future and only assign when we care.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (likely(seconds < 0xc0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) alrm->time.tm_sec = ds1685_rtc_bcd2bin(rtc, seconds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) RTC_SECS_BCD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) RTC_SECS_BIN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (likely(minutes < 0xc0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) alrm->time.tm_min = ds1685_rtc_bcd2bin(rtc, minutes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) RTC_MINS_BCD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) RTC_MINS_BIN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (likely(hours < 0xc0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) alrm->time.tm_hour = ds1685_rtc_bcd2bin(rtc, hours,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) RTC_HRS_24_BCD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) RTC_HRS_24_BIN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* Write the data to rtc_wkalrm. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) alrm->time.tm_mday = ds1685_rtc_bcd2bin(rtc, mday, RTC_MDAY_BCD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) RTC_MDAY_BIN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) alrm->enabled = !!(ctrlb & RTC_CTRL_B_AIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) alrm->pending = !!(ctrlc & RTC_CTRL_C_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * ds1685_rtc_set_alarm - sets the alarm in registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * @dev: pointer to device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * @alrm: pointer to rtc_wkalrm structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct ds1685_priv *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u8 ctrlb, seconds, minutes, hours, mday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* Fetch the alarm info and convert to BCD. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) seconds = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_sec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) RTC_SECS_BIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) RTC_SECS_BCD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) minutes = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) RTC_MINS_BIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) RTC_MINS_BCD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) hours = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_hour,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) RTC_HRS_24_BIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) RTC_HRS_24_BCD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) mday = ds1685_rtc_bin2bcd(rtc, alrm->time.tm_mday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) RTC_MDAY_BIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) RTC_MDAY_BCD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Check the month date for validity. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = ds1685_rtc_check_mday(rtc, mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * Check the three alarm bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * The Linux RTC system doesn't support the "don't care" capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * of this RTC chip because rtc_valid_tm tries to validate every
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * field, and we only support four fields. We put the support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * here anyways for the future.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (unlikely(seconds >= 0xc0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) seconds = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (unlikely(minutes >= 0xc0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) minutes = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (unlikely(hours >= 0xc0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) hours = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) alrm->time.tm_mon = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) alrm->time.tm_year = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) alrm->time.tm_wday = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) alrm->time.tm_yday = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) alrm->time.tm_isdst = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Disable the alarm interrupt first. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ds1685_rtc_begin_data_access(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ctrlb = rtc->read(rtc, RTC_CTRL_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) rtc->write(rtc, RTC_CTRL_B, (ctrlb & ~(RTC_CTRL_B_AIE)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Read ctrlc to clear RTC_CTRL_C_AF. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) rtc->read(rtc, RTC_CTRL_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * Set the data mode to use and store the time values in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * RTC registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ctrlb = rtc->read(rtc, RTC_CTRL_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (rtc->bcd_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ctrlb &= ~(RTC_CTRL_B_DM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ctrlb |= RTC_CTRL_B_DM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) rtc->write(rtc, RTC_CTRL_B, ctrlb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) rtc->write(rtc, RTC_SECS_ALARM, seconds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) rtc->write(rtc, RTC_MINS_ALARM, minutes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) rtc->write(rtc, RTC_HRS_ALARM, hours);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) rtc->write(rtc, RTC_MDAY_ALARM, mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Re-enable the alarm if needed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (alrm->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ctrlb = rtc->read(rtc, RTC_CTRL_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ctrlb |= RTC_CTRL_B_AIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) rtc->write(rtc, RTC_CTRL_B, ctrlb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* Done! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ds1685_rtc_end_data_access(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* /dev/rtcX Interface functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * ds1685_rtc_alarm_irq_enable - replaces ioctl() RTC_AIE on/off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * @dev: pointer to device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * @enabled: flag indicating whether to enable or disable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ds1685_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct ds1685_priv *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* Flip the requisite interrupt-enable bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) RTC_CTRL_B_AIE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) rtc->write(rtc, RTC_CTRL_B, (rtc->read(rtc, RTC_CTRL_B) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ~(RTC_CTRL_B_AIE)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Read Control C to clear all the flag bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) rtc->read(rtc, RTC_CTRL_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* IRQ handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * ds1685_rtc_extended_irq - take care of extended interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * @rtc: pointer to the ds1685 rtc structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * @pdev: platform device pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ds1685_rtc_extended_irq(struct ds1685_priv *rtc, struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u8 ctrl4a, ctrl4b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ds1685_rtc_switch_to_bank1(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * Check for a kickstart interrupt. With Vcc applied, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * typically means that the power button was pressed, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * begin the shutdown sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if ((ctrl4b & RTC_CTRL_4B_KSE) && (ctrl4a & RTC_CTRL_4A_KF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Briefly disable kickstarts to debounce button presses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) rtc->write(rtc, RTC_EXT_CTRL_4B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) (rtc->read(rtc, RTC_EXT_CTRL_4B) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ~(RTC_CTRL_4B_KSE)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* Clear the kickstart flag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) rtc->write(rtc, RTC_EXT_CTRL_4A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) (ctrl4a & ~(RTC_CTRL_4A_KF)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * Sleep 500ms before re-enabling kickstarts. This allows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * adequate time to avoid reading signal jitter as additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * button presses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) msleep(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) rtc->write(rtc, RTC_EXT_CTRL_4B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) (rtc->read(rtc, RTC_EXT_CTRL_4B) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) RTC_CTRL_4B_KSE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* Call the platform pre-poweroff function. Else, shutdown. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (rtc->prepare_poweroff != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) rtc->prepare_poweroff();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ds1685_rtc_poweroff(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * Check for a wake-up interrupt. With Vcc applied, this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * essentially a second alarm interrupt, except it takes into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * account the 'date' register in bank1 in addition to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * standard three alarm registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if ((ctrl4b & RTC_CTRL_4B_WIE) && (ctrl4a & RTC_CTRL_4A_WF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) rtc->write(rtc, RTC_EXT_CTRL_4A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) (ctrl4a & ~(RTC_CTRL_4A_WF)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* Call the platform wake_alarm function if defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (rtc->wake_alarm != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) rtc->wake_alarm();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) "Wake Alarm IRQ just occurred!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * Check for a ram-clear interrupt. This happens if RIE=1 and RF=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * when RCE=1 in 4B. This clears all NVRAM bytes in bank0 by setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * each byte to a logic 1. This has no effect on any extended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * NV-SRAM that might be present, nor on the time/calendar/alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * registers. After a ram-clear is completed, there is a minimum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * recovery time of ~150ms in which all reads/writes are locked out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * NOTE: A ram-clear can still occur if RCE=1 and RIE=0. We cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * catch this scenario.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if ((ctrl4b & RTC_CTRL_4B_RIE) && (ctrl4a & RTC_CTRL_4A_RF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) rtc->write(rtc, RTC_EXT_CTRL_4A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) (ctrl4a & ~(RTC_CTRL_4A_RF)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) msleep(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Call the platform post_ram_clear function if defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (rtc->post_ram_clear != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) rtc->post_ram_clear();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) "RAM-Clear IRQ just occurred!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ds1685_rtc_switch_to_bank0(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * ds1685_rtc_irq_handler - IRQ handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * @irq: IRQ number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * @dev_id: platform device pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ds1685_rtc_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct platform_device *pdev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct ds1685_priv *rtc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct mutex *rtc_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u8 ctrlb, ctrlc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) unsigned long events = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) u8 num_irqs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* Abort early if the device isn't ready yet (i.e., DEBUG_SHIRQ). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (unlikely(!rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) rtc_mutex = &rtc->dev->ops_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) mutex_lock(rtc_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* Ctrlb holds the interrupt-enable bits and ctrlc the flag bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ctrlb = rtc->read(rtc, RTC_CTRL_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ctrlc = rtc->read(rtc, RTC_CTRL_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Is the IRQF bit set? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (likely(ctrlc & RTC_CTRL_C_IRQF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * We need to determine if it was one of the standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * events: PF, AF, or UF. If so, we handle them and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * update the RTC core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (likely(ctrlc & RTC_CTRL_B_PAU_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) events = RTC_IRQF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* Check for a periodic interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if ((ctrlb & RTC_CTRL_B_PIE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) (ctrlc & RTC_CTRL_C_PF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) events |= RTC_PF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) num_irqs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* Check for an alarm interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if ((ctrlb & RTC_CTRL_B_AIE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) (ctrlc & RTC_CTRL_C_AF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) events |= RTC_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) num_irqs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* Check for an update interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if ((ctrlb & RTC_CTRL_B_UIE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) (ctrlc & RTC_CTRL_C_UF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) events |= RTC_UF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) num_irqs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * One of the "extended" interrupts was received that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * is not recognized by the RTC core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ds1685_rtc_extended_irq(rtc, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) rtc_update_irq(rtc->dev, num_irqs, events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) mutex_unlock(rtc_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return events ? IRQ_HANDLED : IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* ProcFS interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define NUM_REGS 6 /* Num of control registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define NUM_BITS 8 /* Num bits per register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define NUM_SPACES 4 /* Num spaces between each bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * Periodic Interrupt Rates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static const char *ds1685_rtc_pirq_rate[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) "none", "3.90625ms", "7.8125ms", "0.122070ms", "0.244141ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) "0.488281ms", "0.9765625ms", "1.953125ms", "3.90625ms", "7.8125ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) "15.625ms", "31.25ms", "62.5ms", "125ms", "250ms", "500ms"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * Square-Wave Output Frequencies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static const char *ds1685_rtc_sqw_freq[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) "none", "256Hz", "128Hz", "8192Hz", "4096Hz", "2048Hz", "1024Hz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) "512Hz", "256Hz", "128Hz", "64Hz", "32Hz", "16Hz", "8Hz", "4Hz", "2Hz"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * ds1685_rtc_proc - procfs access function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * @dev: pointer to device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * @seq: pointer to seq_file structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ds1685_rtc_proc(struct device *dev, struct seq_file *seq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct ds1685_priv *rtc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) u8 ctrla, ctrlb, ctrld, ctrl4a, ctrl4b, ssn[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) char *model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* Read all the relevant data from the control registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) ds1685_rtc_switch_to_bank1(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ds1685_rtc_get_ssn(rtc, ssn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ctrla = rtc->read(rtc, RTC_CTRL_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ctrlb = rtc->read(rtc, RTC_CTRL_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ctrld = rtc->read(rtc, RTC_CTRL_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ds1685_rtc_switch_to_bank0(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* Determine the RTC model. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) switch (ssn[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) case RTC_MODEL_DS1685:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) model = "DS1685/DS1687\0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) case RTC_MODEL_DS1689:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) model = "DS1689/DS1693\0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) case RTC_MODEL_DS17285:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) model = "DS17285/DS17287\0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) case RTC_MODEL_DS17485:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) model = "DS17485/DS17487\0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) case RTC_MODEL_DS17885:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) model = "DS17885/DS17887\0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) model = "Unknown\0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* Print out the information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) seq_printf(seq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) "Model\t\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) "Oscillator\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) "12/24hr\t\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) "DST\t\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) "Data mode\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) "Battery\t\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) "Aux batt\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) "Update IRQ\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) "Periodic IRQ\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) "Periodic Rate\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) "SQW Freq\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) "Serial #\t: %8phC\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) model,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ((ctrla & RTC_CTRL_A_DV1) ? "enabled" : "disabled"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ((ctrlb & RTC_CTRL_B_2412) ? "24-hour" : "12-hour"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ((ctrlb & RTC_CTRL_B_DSE) ? "enabled" : "disabled"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ((ctrlb & RTC_CTRL_B_DM) ? "binary" : "BCD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ((ctrld & RTC_CTRL_D_VRT) ? "ok" : "exhausted or n/a"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ((ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "exhausted or n/a"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ((ctrlb & RTC_CTRL_B_UIE) ? "yes" : "no"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ((ctrlb & RTC_CTRL_B_PIE) ? "yes" : "no"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) (!(ctrl4b & RTC_CTRL_4B_E32K) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) ds1685_rtc_pirq_rate[(ctrla & RTC_CTRL_A_RS_MASK)] : "none"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) (!((ctrl4b & RTC_CTRL_4B_E32K)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ds1685_rtc_sqw_freq[(ctrla & RTC_CTRL_A_RS_MASK)] : "32768Hz"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ssn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define ds1685_rtc_proc NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #endif /* CONFIG_PROC_FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* RTC Class operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static const struct rtc_class_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ds1685_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .proc = ds1685_rtc_proc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .read_time = ds1685_rtc_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .set_time = ds1685_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .read_alarm = ds1685_rtc_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .set_alarm = ds1685_rtc_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .alarm_irq_enable = ds1685_rtc_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static int ds1685_nvram_read(void *priv, unsigned int pos, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) struct ds1685_priv *rtc = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct mutex *rtc_mutex = &rtc->dev->ops_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ssize_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) u8 *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) err = mutex_lock_interruptible(rtc_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ds1685_rtc_switch_to_bank0(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* Read NVRAM in time and bank0 registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) count++, size--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (count < NVRAM_SZ_TIME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) *buf++ = rtc->read(rtc, (NVRAM_TIME_BASE + pos++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) *buf++ = rtc->read(rtc, (NVRAM_BANK0_BASE + pos++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #ifndef CONFIG_RTC_DRV_DS1689
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ds1685_rtc_switch_to_bank1(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #ifndef CONFIG_RTC_DRV_DS1685
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* Enable burst-mode on DS17x85/DS17x87 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) rtc->write(rtc, RTC_EXT_CTRL_4A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) (rtc->read(rtc, RTC_EXT_CTRL_4A) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) RTC_CTRL_4A_BME));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * reading with burst-mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) (pos - NVRAM_TOTAL_SZ_BANK0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* Read NVRAM in bank1 registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) count++, size--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #ifdef CONFIG_RTC_DRV_DS1685
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * before each read. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) rtc->write(rtc, RTC_BANK1_RAM_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) (pos - NVRAM_TOTAL_SZ_BANK0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) *buf++ = rtc->read(rtc, RTC_BANK1_RAM_DATA_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) pos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #ifndef CONFIG_RTC_DRV_DS1685
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* Disable burst-mode on DS17x85/DS17x87 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) rtc->write(rtc, RTC_EXT_CTRL_4A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) (rtc->read(rtc, RTC_EXT_CTRL_4A) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) ~(RTC_CTRL_4A_BME)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ds1685_rtc_switch_to_bank0(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #endif /* !CONFIG_RTC_DRV_DS1689 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) mutex_unlock(rtc_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static int ds1685_nvram_write(void *priv, unsigned int pos, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct ds1685_priv *rtc = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct mutex *rtc_mutex = &rtc->dev->ops_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ssize_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) u8 *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) err = mutex_lock_interruptible(rtc_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ds1685_rtc_switch_to_bank0(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* Write NVRAM in time and bank0 registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ_BANK0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) count++, size--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (count < NVRAM_SZ_TIME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) rtc->write(rtc, (NVRAM_TIME_BASE + pos++),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) *buf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) rtc->write(rtc, (NVRAM_BANK0_BASE), *buf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #ifndef CONFIG_RTC_DRV_DS1689
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) ds1685_rtc_switch_to_bank1(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #ifndef CONFIG_RTC_DRV_DS1685
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /* Enable burst-mode on DS17x85/DS17x87 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) rtc->write(rtc, RTC_EXT_CTRL_4A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) (rtc->read(rtc, RTC_EXT_CTRL_4A) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) RTC_CTRL_4A_BME));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* We need one write to RTC_BANK1_RAM_ADDR_LSB to start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * writing with burst-mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) rtc->write(rtc, RTC_BANK1_RAM_ADDR_LSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) (pos - NVRAM_TOTAL_SZ_BANK0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* Write NVRAM in bank1 registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) for (count = 0; size > 0 && pos < NVRAM_TOTAL_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) count++, size--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #ifdef CONFIG_RTC_DRV_DS1685
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* DS1685/DS1687 has to write to RTC_BANK1_RAM_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * before each read. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) rtc->write(rtc, RTC_BANK1_RAM_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) (pos - NVRAM_TOTAL_SZ_BANK0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) rtc->write(rtc, RTC_BANK1_RAM_DATA_PORT, *buf++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) pos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #ifndef CONFIG_RTC_DRV_DS1685
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /* Disable burst-mode on DS17x85/DS17x87 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) rtc->write(rtc, RTC_EXT_CTRL_4A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) (rtc->read(rtc, RTC_EXT_CTRL_4A) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) ~(RTC_CTRL_4A_BME)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) ds1685_rtc_switch_to_bank0(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #endif /* !CONFIG_RTC_DRV_DS1689 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) mutex_unlock(rtc_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* SysFS interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * ds1685_rtc_sysfs_battery_show - sysfs file for main battery status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * @dev: pointer to device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * @attr: pointer to device_attribute structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * @buf: pointer to char array to hold the output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) ds1685_rtc_sysfs_battery_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct ds1685_priv *rtc = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) u8 ctrld;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ctrld = rtc->read(rtc, RTC_CTRL_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return sprintf(buf, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) (ctrld & RTC_CTRL_D_VRT) ? "ok" : "not ok or N/A");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static DEVICE_ATTR(battery, S_IRUGO, ds1685_rtc_sysfs_battery_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * ds1685_rtc_sysfs_auxbatt_show - sysfs file for aux battery status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * @dev: pointer to device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * @attr: pointer to device_attribute structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * @buf: pointer to char array to hold the output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) ds1685_rtc_sysfs_auxbatt_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct ds1685_priv *rtc = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) u8 ctrl4a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) ds1685_rtc_switch_to_bank1(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ds1685_rtc_switch_to_bank0(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return sprintf(buf, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) (ctrl4a & RTC_CTRL_4A_VRT2) ? "ok" : "not ok or N/A");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static DEVICE_ATTR(auxbatt, S_IRUGO, ds1685_rtc_sysfs_auxbatt_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * ds1685_rtc_sysfs_serial_show - sysfs file for silicon serial number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * @dev: pointer to device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * @attr: pointer to device_attribute structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) * @buf: pointer to char array to hold the output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ds1685_rtc_sysfs_serial_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct ds1685_priv *rtc = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) u8 ssn[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) ds1685_rtc_switch_to_bank1(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) ds1685_rtc_get_ssn(rtc, ssn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) ds1685_rtc_switch_to_bank0(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return sprintf(buf, "%8phC\n", ssn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static DEVICE_ATTR(serial, S_IRUGO, ds1685_rtc_sysfs_serial_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * struct ds1685_rtc_sysfs_misc_attrs - list for misc RTC features.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static struct attribute*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ds1685_rtc_sysfs_misc_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) &dev_attr_battery.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) &dev_attr_auxbatt.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) &dev_attr_serial.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) * struct ds1685_rtc_sysfs_misc_grp - attr group for misc RTC features.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static const struct attribute_group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) ds1685_rtc_sysfs_misc_grp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .name = "misc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .attrs = ds1685_rtc_sysfs_misc_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* Driver Probe/Removal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * ds1685_rtc_probe - initializes rtc driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * @pdev: pointer to platform_device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) ds1685_rtc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct rtc_device *rtc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) struct ds1685_priv *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) struct ds1685_rtc_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) u8 ctrla, ctrlb, hours;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) unsigned char am_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) struct nvmem_config nvmem_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .name = "ds1685_nvram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .size = NVRAM_TOTAL_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .reg_read = ds1685_nvram_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .reg_write = ds1685_nvram_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) /* Get the platform data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) pdata = (struct ds1685_rtc_platform_data *) pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /* Allocate memory for the rtc device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (!rtc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) /* Setup resources and access functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) switch (pdata->access_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) case ds1685_reg_direct:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) rtc->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (IS_ERR(rtc->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return PTR_ERR(rtc->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) rtc->read = ds1685_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) rtc->write = ds1685_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) case ds1685_reg_indirect:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) rtc->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (IS_ERR(rtc->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return PTR_ERR(rtc->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) rtc->data = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (IS_ERR(rtc->data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return PTR_ERR(rtc->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) rtc->read = ds1685_indirect_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) rtc->write = ds1685_indirect_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) if (!rtc->read || !rtc->write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /* Get the register step size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (pdata->regstep > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) rtc->regstep = pdata->regstep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) rtc->regstep = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) /* Platform pre-shutdown function, if defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (pdata->plat_prepare_poweroff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) rtc->prepare_poweroff = pdata->plat_prepare_poweroff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) /* Platform wake_alarm function, if defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (pdata->plat_wake_alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) rtc->wake_alarm = pdata->plat_wake_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* Platform post_ram_clear function, if defined. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (pdata->plat_post_ram_clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) rtc->post_ram_clear = pdata->plat_post_ram_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) /* set the driver data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) platform_set_drvdata(pdev, rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /* Turn the oscillator on if is not already on (DV1 = 1). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) ctrla = rtc->read(rtc, RTC_CTRL_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (!(ctrla & RTC_CTRL_A_DV1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) ctrla |= RTC_CTRL_A_DV1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /* Enable the countdown chain (DV2 = 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) ctrla &= ~(RTC_CTRL_A_DV2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /* Clear RS3-RS0 in Control A. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) ctrla &= ~(RTC_CTRL_A_RS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) * All done with Control A. Switch to Bank 1 for the remainder of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * the RTC setup so we have access to the extended functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) ctrla |= RTC_CTRL_A_DV0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) rtc->write(rtc, RTC_CTRL_A, ctrla);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) /* Default to 32768kHz output. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) rtc->write(rtc, RTC_EXT_CTRL_4B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_E32K));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /* Set the SET bit in Control B so we can do some housekeeping. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) rtc->write(rtc, RTC_CTRL_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) (rtc->read(rtc, RTC_CTRL_B) | RTC_CTRL_B_SET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /* Read Ext Ctrl 4A and check the INCR bit to avoid a lockout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) while (rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_INCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * If the platform supports BCD mode, then set DM=0 in Control B.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * Otherwise, set DM=1 for BIN mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ctrlb = rtc->read(rtc, RTC_CTRL_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (pdata->bcd_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) ctrlb &= ~(RTC_CTRL_B_DM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ctrlb |= RTC_CTRL_B_DM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) rtc->bcd_mode = pdata->bcd_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * Disable Daylight Savings Time (DSE = 0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) * The RTC has hardcoded timezone information that is rendered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) * obselete. We'll let the OS deal with DST settings instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (ctrlb & RTC_CTRL_B_DSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) ctrlb &= ~(RTC_CTRL_B_DSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /* Force 24-hour mode (2412 = 1). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (!(ctrlb & RTC_CTRL_B_2412)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) /* Reinitialize the time hours. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) hours = rtc->read(rtc, RTC_HRS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) am_pm = hours & RTC_HRS_AMPM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) RTC_HRS_12_BIN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) /* Enable 24-hour mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) ctrlb |= RTC_CTRL_B_2412;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /* Write back to Control B, including DM & DSE bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) rtc->write(rtc, RTC_CTRL_B, ctrlb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /* Write the time hours back. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) rtc->write(rtc, RTC_HRS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) ds1685_rtc_bin2bcd(rtc, hours,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) RTC_HRS_24_BIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) RTC_HRS_24_BCD_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) /* Reinitialize the alarm hours. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) hours = rtc->read(rtc, RTC_HRS_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) am_pm = hours & RTC_HRS_AMPM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) hours = ds1685_rtc_bcd2bin(rtc, hours, RTC_HRS_12_BCD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) RTC_HRS_12_BIN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) hours = ((hours == 12) ? 0 : ((am_pm) ? hours + 12 : hours));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) /* Write the alarm hours back. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) rtc->write(rtc, RTC_HRS_ALARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) ds1685_rtc_bin2bcd(rtc, hours,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) RTC_HRS_24_BIN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) RTC_HRS_24_BCD_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /* 24-hour mode is already set, so write Control B back. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) rtc->write(rtc, RTC_CTRL_B, ctrlb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) /* Unset the SET bit in Control B so the RTC can update. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) rtc->write(rtc, RTC_CTRL_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_SET)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /* Check the main battery. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (!(rtc->read(rtc, RTC_CTRL_D) & RTC_CTRL_D_VRT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) "Main battery is exhausted! RTC may be invalid!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) /* Check the auxillary battery. It is optional. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (!(rtc->read(rtc, RTC_EXT_CTRL_4A) & RTC_CTRL_4A_VRT2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) "Aux battery is exhausted or not available.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* Read Ctrl B and clear PIE/AIE/UIE. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) rtc->write(rtc, RTC_CTRL_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) (rtc->read(rtc, RTC_CTRL_B) & ~(RTC_CTRL_B_PAU_MASK)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* Reading Ctrl C auto-clears PF/AF/UF. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) rtc->read(rtc, RTC_CTRL_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) /* Read Ctrl 4B and clear RIE/WIE/KSE. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) rtc->write(rtc, RTC_EXT_CTRL_4B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) (rtc->read(rtc, RTC_EXT_CTRL_4B) & ~(RTC_CTRL_4B_RWK_MASK)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) /* Clear RF/WF/KF in Ctrl 4A. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) rtc->write(rtc, RTC_EXT_CTRL_4A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) (rtc->read(rtc, RTC_EXT_CTRL_4A) & ~(RTC_CTRL_4A_RWK_MASK)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) * Re-enable KSE to handle power button events. We do not enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) * WIE or RIE by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) rtc->write(rtc, RTC_EXT_CTRL_4B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) (rtc->read(rtc, RTC_EXT_CTRL_4B) | RTC_CTRL_4B_KSE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) rtc_dev = devm_rtc_allocate_device(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (IS_ERR(rtc_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) return PTR_ERR(rtc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) rtc_dev->ops = &ds1685_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) /* Century bit is useless because leap year fails in 1900 and 2100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) rtc_dev->range_max = RTC_TIMESTAMP_END_2099;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /* Maximum periodic rate is 8192Hz (0.122070ms). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) rtc_dev->max_user_freq = RTC_MAX_USER_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) /* See if the platform doesn't support UIE. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (pdata->uie_unsupported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) rtc_dev->uie_unsupported = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) rtc->dev = rtc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) * Fetch the IRQ and setup the interrupt handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) * Not all platforms have the IRQF pin tied to something. If not, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) * RTC will still set the *IE / *F flags and raise IRQF in ctrlc, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) * there won't be an automatic way of notifying the kernel about it,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) * unless ctrlc is explicitly polled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (!pdata->no_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) rtc->irq_num = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /* Request an IRQ. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) NULL, ds1685_rtc_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) IRQF_SHARED | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) pdev->name, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) /* Check to see if something came back. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (unlikely(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) "RTC interrupt not available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) rtc->irq_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) rtc->no_irq = pdata->no_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /* Setup complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) ds1685_rtc_switch_to_bank0(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) ret = rtc_add_group(rtc_dev, &ds1685_rtc_sysfs_misc_grp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) rtc_dev->nvram_old_abi = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) nvmem_cfg.priv = rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) ret = rtc_nvmem_register(rtc_dev, &nvmem_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) return rtc_register_device(rtc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) * ds1685_rtc_remove - removes rtc driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) * @pdev: pointer to platform_device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) ds1685_rtc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) struct ds1685_priv *rtc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) /* Read Ctrl B and clear PIE/AIE/UIE. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) rtc->write(rtc, RTC_CTRL_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) (rtc->read(rtc, RTC_CTRL_B) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) ~(RTC_CTRL_B_PAU_MASK)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /* Reading Ctrl C auto-clears PF/AF/UF. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) rtc->read(rtc, RTC_CTRL_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) /* Read Ctrl 4B and clear RIE/WIE/KSE. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) rtc->write(rtc, RTC_EXT_CTRL_4B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) (rtc->read(rtc, RTC_EXT_CTRL_4B) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) ~(RTC_CTRL_4B_RWK_MASK)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) /* Manually clear RF/WF/KF in Ctrl 4A. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) rtc->write(rtc, RTC_EXT_CTRL_4A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) (rtc->read(rtc, RTC_EXT_CTRL_4A) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) ~(RTC_CTRL_4A_RWK_MASK)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) * ds1685_rtc_driver - rtc driver properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) static struct platform_driver ds1685_rtc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .name = "rtc-ds1685",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .probe = ds1685_rtc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .remove = ds1685_rtc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) module_platform_driver(ds1685_rtc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) /* Poweroff function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) * ds1685_rtc_poweroff - uses the RTC chip to power the system off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) * @pdev: pointer to platform_device structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) void __noreturn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) ds1685_rtc_poweroff(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) u8 ctrla, ctrl4a, ctrl4b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) struct ds1685_priv *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) /* Check for valid RTC data, else, spin forever. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (unlikely(!pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) pr_emerg("platform device data not available, spinning forever ...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) while(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) unreachable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /* Get the rtc data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) rtc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * Disable our IRQ. We're powering down, so we're not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) * going to worry about cleaning up. Most of that should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) * have been taken care of by the shutdown scripts and this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * is the final function call.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (!rtc->no_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) disable_irq_nosync(rtc->irq_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) /* Oscillator must be on and the countdown chain enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) ctrla = rtc->read(rtc, RTC_CTRL_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) ctrla |= RTC_CTRL_A_DV1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) ctrla &= ~(RTC_CTRL_A_DV2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) rtc->write(rtc, RTC_CTRL_A, ctrla);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) * Read Control 4A and check the status of the auxillary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) * battery. This must be present and working (VRT2 = 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) * for wakeup and kickstart functionality to be useful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) ds1685_rtc_switch_to_bank1(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) ctrl4a = rtc->read(rtc, RTC_EXT_CTRL_4A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (ctrl4a & RTC_CTRL_4A_VRT2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /* Clear all of the interrupt flags on Control 4A. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) ctrl4a &= ~(RTC_CTRL_4A_RWK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) rtc->write(rtc, RTC_EXT_CTRL_4A, ctrl4a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) * The auxillary battery is present and working.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) * Enable extended functions (ABE=1), enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) * wake-up (WIE=1), and enable kickstart (KSE=1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) * in Control 4B.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) ctrl4b = rtc->read(rtc, RTC_EXT_CTRL_4B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) ctrl4b |= (RTC_CTRL_4B_ABE | RTC_CTRL_4B_WIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) RTC_CTRL_4B_KSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) rtc->write(rtc, RTC_EXT_CTRL_4B, ctrl4b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) /* Set PAB to 1 in Control 4A to power the system down. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) dev_warn(&pdev->dev, "Powerdown.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) rtc->write(rtc, RTC_EXT_CTRL_4A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) (ctrl4a | RTC_CTRL_4A_PAB));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) /* Spin ... we do not switch back to bank0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) while(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) unreachable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) EXPORT_SYMBOL(ds1685_rtc_poweroff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) MODULE_AUTHOR("Joshua Kinard <kumba@gentoo.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) MODULE_AUTHOR("Matthias Fuchs <matthias.fuchs@esd-electronics.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) MODULE_DESCRIPTION("Dallas/Maxim DS1685/DS1687-series RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) MODULE_ALIAS("platform:rtc-ds1685");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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