^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * RTC client/driver for the Maxim/Dallas DS1374 Real-Time Clock over I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Based on code by Randy Vinson <rvinson@mvista.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * which was based on the m41t00.c by Mark Greer <mgreer@mvista.com>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2014 Rose Technology
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2006-2007 Freescale Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 2005 (c) MontaVista Software, Inc. This file is licensed under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * the terms of the GNU General Public License version 2. This program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * is licensed "as is" without any warranty of any kind, whether express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * It would be more efficient to use i2c msgs/i2c_transfer directly but, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * recommended in .../Documentation/i2c/writing-clients.rst section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * "Sending and receiving", using SMBus level communication is preferred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifdef CONFIG_RTC_DRV_DS1374_WDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/ioctl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/miscdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DS1374_REG_TOD0 0x00 /* Time of Day */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DS1374_REG_TOD1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DS1374_REG_TOD2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DS1374_REG_TOD3 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DS1374_REG_WDALM0 0x04 /* Watchdog/Alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DS1374_REG_WDALM1 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DS1374_REG_WDALM2 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DS1374_REG_CR 0x07 /* Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DS1374_REG_CR_AIE 0x01 /* Alarm Int. Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DS1374_REG_CR_WDSTR 0x08 /* 1=INT, 0=RST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DS1374_REG_CR_WDALM 0x20 /* 1=Watchdog, 0=Alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DS1374_REG_CR_WACE 0x40 /* WD/Alarm counter enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DS1374_REG_SR 0x08 /* Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DS1374_REG_SR_OSF 0x80 /* Oscillator Stop Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DS1374_REG_SR_AF 0x01 /* Alarm Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DS1374_REG_TCR 0x09 /* Trickle Charge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const struct i2c_device_id ds1374_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { "ds1374", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MODULE_DEVICE_TABLE(i2c, ds1374_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const struct of_device_id ds1374_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { .compatible = "dallas,ds1374" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MODULE_DEVICE_TABLE(of, ds1374_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct ds1374 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #ifdef CONFIG_RTC_DRV_DS1374_WDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct watchdog_device wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* The mutex protects alarm operations, and prevents a race
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * between the enable_irq() in the workqueue and the free_irq()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * in the remove function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int exiting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct i2c_driver ds1374_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int ds1374_read_rtc(struct i2c_client *client, u32 *time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int reg, int nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (WARN_ON(nbytes > 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ret = i2c_smbus_read_i2c_block_data(client, reg, nbytes, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (ret < nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) for (i = nbytes - 1, *time = 0; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *time = (*time << 8) | buf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int ds1374_write_rtc(struct i2c_client *client, u32 time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int reg, int nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u8 buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (nbytes > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) for (i = 0; i < nbytes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) buf[i] = time & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) time >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return i2c_smbus_write_i2c_block_data(client, reg, nbytes, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int ds1374_check_rtc_status(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int control, stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) stat = i2c_smbus_read_byte_data(client, DS1374_REG_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (stat < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (stat & DS1374_REG_SR_OSF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dev_warn(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "oscillator discontinuity flagged, time unreliable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) stat &= ~(DS1374_REG_SR_OSF | DS1374_REG_SR_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ret = i2c_smbus_write_byte_data(client, DS1374_REG_SR, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* If the alarm is pending, clear it before requesting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * the interrupt, so an interrupt event isn't reported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * before everything is initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) control = i2c_smbus_read_byte_data(client, DS1374_REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (control < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) control &= ~(DS1374_REG_CR_WACE | DS1374_REG_CR_AIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return i2c_smbus_write_byte_data(client, DS1374_REG_CR, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int ds1374_read_time(struct device *dev, struct rtc_time *time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 itime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ret = ds1374_read_rtc(client, &itime, DS1374_REG_TOD0, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) rtc_time64_to_tm(itime, time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int ds1374_set_time(struct device *dev, struct rtc_time *time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned long itime = rtc_tm_to_time64(time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return ds1374_write_rtc(client, itime, DS1374_REG_TOD0, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #ifndef CONFIG_RTC_DRV_DS1374_WDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* The ds1374 has a decrementer for an alarm, rather than a comparator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * If the time of day is changed, then the alarm will need to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int ds1374_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct ds1374 *ds1374 = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 now, cur_alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int cr, sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (client->irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) mutex_lock(&ds1374->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) cr = ret = i2c_smbus_read_byte_data(client, DS1374_REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) sr = ret = i2c_smbus_read_byte_data(client, DS1374_REG_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ret = ds1374_read_rtc(client, &now, DS1374_REG_TOD0, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ret = ds1374_read_rtc(client, &cur_alarm, DS1374_REG_WDALM0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) rtc_time64_to_tm(now + cur_alarm, &alarm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) alarm->enabled = !!(cr & DS1374_REG_CR_WACE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) alarm->pending = !!(sr & DS1374_REG_SR_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) mutex_unlock(&ds1374->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int ds1374_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct ds1374 *ds1374 = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct rtc_time now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned long new_alarm, itime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (client->irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = ds1374_read_time(dev, &now);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) new_alarm = rtc_tm_to_time64(&alarm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) itime = rtc_tm_to_time64(&now);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* This can happen due to races, in addition to dates that are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * truly in the past. To avoid requiring the caller to check for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * races, dates in the past are assumed to be in the recent past
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * (i.e. not something that we'd rather the caller know about via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * an error), and the alarm is set to go off as soon as possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (time_before_eq(new_alarm, itime))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) new_alarm = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) new_alarm -= itime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) mutex_lock(&ds1374->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = cr = i2c_smbus_read_byte_data(client, DS1374_REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Disable any existing alarm before setting the new one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * (or lack thereof). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) cr &= ~DS1374_REG_CR_WACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ret = i2c_smbus_write_byte_data(client, DS1374_REG_CR, cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ret = ds1374_write_rtc(client, new_alarm, DS1374_REG_WDALM0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (alarm->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) cr |= DS1374_REG_CR_WACE | DS1374_REG_CR_AIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) cr &= ~DS1374_REG_CR_WDALM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ret = i2c_smbus_write_byte_data(client, DS1374_REG_CR, cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) mutex_unlock(&ds1374->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static irqreturn_t ds1374_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct i2c_client *client = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct ds1374 *ds1374 = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) disable_irq_nosync(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) schedule_work(&ds1374->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static void ds1374_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct ds1374 *ds1374 = container_of(work, struct ds1374, work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct i2c_client *client = ds1374->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int stat, control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) mutex_lock(&ds1374->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) stat = i2c_smbus_read_byte_data(client, DS1374_REG_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (stat < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (stat & DS1374_REG_SR_AF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) stat &= ~DS1374_REG_SR_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) i2c_smbus_write_byte_data(client, DS1374_REG_SR, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) control = i2c_smbus_read_byte_data(client, DS1374_REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (control < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) control &= ~(DS1374_REG_CR_WACE | DS1374_REG_CR_AIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) i2c_smbus_write_byte_data(client, DS1374_REG_CR, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) rtc_update_irq(ds1374->rtc, 1, RTC_AF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (!ds1374->exiting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) enable_irq(client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) mutex_unlock(&ds1374->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #ifndef CONFIG_RTC_DRV_DS1374_WDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static int ds1374_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct ds1374 *ds1374 = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) mutex_lock(&ds1374->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ret = i2c_smbus_read_byte_data(client, DS1374_REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ret |= DS1374_REG_CR_WACE | DS1374_REG_CR_AIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ret &= ~DS1374_REG_CR_WDALM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ret &= ~DS1374_REG_CR_WACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ret = i2c_smbus_write_byte_data(client, DS1374_REG_CR, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) mutex_unlock(&ds1374->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static const struct rtc_class_ops ds1374_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .read_time = ds1374_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .set_time = ds1374_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #ifndef CONFIG_RTC_DRV_DS1374_WDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .read_alarm = ds1374_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .set_alarm = ds1374_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .alarm_irq_enable = ds1374_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #ifdef CONFIG_RTC_DRV_DS1374_WDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * Watchdog Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Default margin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define TIMER_MARGIN_DEFAULT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define TIMER_MARGIN_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define TIMER_MARGIN_MAX 4095 /* 24-bit value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int wdt_margin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) module_param(wdt_margin, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MODULE_PARM_DESC(wdt_margin, "Watchdog timeout in seconds (default 32s)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static bool nowayout = WATCHDOG_NOWAYOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) module_param(nowayout, bool, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default ="
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) __MODULE_STRING(WATCHDOG_NOWAYOUT)")");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const struct watchdog_info ds1374_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .identity = "DS1374 Watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) WDIOF_MAGICCLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int ds1374_wdt_settimeout(struct watchdog_device *wdt, unsigned int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct ds1374 *ds1374 = watchdog_get_drvdata(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct i2c_client *client = ds1374->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int ret, cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) wdt->timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) cr = i2c_smbus_read_byte_data(client, DS1374_REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (cr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Disable any existing watchdog/alarm before setting the new one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) cr &= ~DS1374_REG_CR_WACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ret = i2c_smbus_write_byte_data(client, DS1374_REG_CR, cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Set new watchdog time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) timeout = timeout * 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ret = ds1374_write_rtc(client, timeout, DS1374_REG_WDALM0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* Enable watchdog timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) cr |= DS1374_REG_CR_WACE | DS1374_REG_CR_WDALM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) cr &= ~DS1374_REG_CR_WDSTR;/* for RST PIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) cr &= ~DS1374_REG_CR_AIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ret = i2c_smbus_write_byte_data(client, DS1374_REG_CR, cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * Reload the watchdog timer. (ie, pat the watchdog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int ds1374_wdt_start(struct watchdog_device *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct ds1374 *ds1374 = watchdog_get_drvdata(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return ds1374_read_rtc(ds1374->client, &val, DS1374_REG_WDALM0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int ds1374_wdt_stop(struct watchdog_device *wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct ds1374 *ds1374 = watchdog_get_drvdata(wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct i2c_client *client = ds1374->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) cr = i2c_smbus_read_byte_data(client, DS1374_REG_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (cr < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* Disable watchdog timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) cr &= ~DS1374_REG_CR_WACE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return i2c_smbus_write_byte_data(client, DS1374_REG_CR, cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static const struct watchdog_ops ds1374_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .start = ds1374_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .stop = ds1374_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .set_timeout = ds1374_wdt_settimeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #endif /*CONFIG_RTC_DRV_DS1374_WDT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * Driver Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) *****************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static int ds1374_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct ds1374 *ds1374;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ds1374 = devm_kzalloc(&client->dev, sizeof(struct ds1374), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (!ds1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ds1374->rtc = devm_rtc_allocate_device(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (IS_ERR(ds1374->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return PTR_ERR(ds1374->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ds1374->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) i2c_set_clientdata(client, ds1374);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) INIT_WORK(&ds1374->work, ds1374_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) mutex_init(&ds1374->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = ds1374_check_rtc_status(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (client->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ret = devm_request_irq(&client->dev, client->irq, ds1374_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) "ds1374", client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dev_err(&client->dev, "unable to request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) device_set_wakeup_capable(&client->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ds1374->rtc->ops = &ds1374_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ds1374->rtc->range_max = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ret = rtc_register_device(ds1374->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #ifdef CONFIG_RTC_DRV_DS1374_WDT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ds1374->wdt.info = &ds1374_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ds1374->wdt.ops = &ds1374_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ds1374->wdt.timeout = TIMER_MARGIN_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ds1374->wdt.min_timeout = TIMER_MARGIN_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ds1374->wdt.max_timeout = TIMER_MARGIN_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) watchdog_init_timeout(&ds1374->wdt, wdt_margin, &client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) watchdog_set_nowayout(&ds1374->wdt, nowayout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) watchdog_stop_on_reboot(&ds1374->wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) watchdog_stop_on_unregister(&ds1374->wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) watchdog_set_drvdata(&ds1374->wdt, ds1374);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ds1374_wdt_settimeout(&ds1374->wdt, ds1374->wdt.timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ret = devm_watchdog_register_device(&client->dev, &ds1374->wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static int ds1374_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct ds1374 *ds1374 = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (client->irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) mutex_lock(&ds1374->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ds1374->exiting = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) mutex_unlock(&ds1374->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) devm_free_irq(&client->dev, client->irq, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) cancel_work_sync(&ds1374->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static int ds1374_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (client->irq > 0 && device_may_wakeup(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) enable_irq_wake(client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static int ds1374_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (client->irq > 0 && device_may_wakeup(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) disable_irq_wake(client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static SIMPLE_DEV_PM_OPS(ds1374_pm, ds1374_suspend, ds1374_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static struct i2c_driver ds1374_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .name = "rtc-ds1374",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .of_match_table = of_match_ptr(ds1374_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .pm = &ds1374_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .probe = ds1374_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .remove = ds1374_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .id_table = ds1374_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) module_i2c_driver(ds1374_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) MODULE_AUTHOR("Scott Wood <scottwood@freescale.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) MODULE_DESCRIPTION("Maxim/Dallas DS1374 RTC Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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