Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* rtc-ds1347.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Driver for Dallas Semiconductor DS1347 Low Current, SPI Compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Real Time Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author : Raghavendra Chandra Ganiga <ravi23ganiga@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* Registers in ds1347 rtc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define DS1347_SECONDS_REG	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define DS1347_MINUTES_REG	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define DS1347_HOURS_REG	0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define DS1347_DATE_REG		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define DS1347_MONTH_REG	0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DS1347_DAY_REG		0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define DS1347_YEAR_REG		0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DS1347_CONTROL_REG	0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DS1347_CENTURY_REG	0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define DS1347_STATUS_REG	0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define DS1347_CLOCK_BURST	0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define DS1347_WP_BIT		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DS1347_NEOSC_BIT	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DS1347_OSF_BIT		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static const struct regmap_range ds1347_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		.range_min = DS1347_SECONDS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		.range_max = DS1347_STATUS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static const struct regmap_access_table ds1347_access_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	.yes_ranges = ds1347_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	.n_yes_ranges = ARRAY_SIZE(ds1347_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static int ds1347_read_time(struct device *dev, struct rtc_time *dt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct regmap *map = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	unsigned int status, century, secs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	unsigned char buf[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	err = regmap_read(map, DS1347_STATUS_REG, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	if (status & DS1347_OSF_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		err = regmap_bulk_read(map, DS1347_CLOCK_BURST, buf, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		err = regmap_read(map, DS1347_CENTURY_REG, &century);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		err = regmap_read(map, DS1347_SECONDS_REG, &secs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	} while (buf[0] != secs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	dt->tm_sec = bcd2bin(buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	dt->tm_min = bcd2bin(buf[1] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	dt->tm_hour = bcd2bin(buf[2] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	dt->tm_mday = bcd2bin(buf[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	dt->tm_mon = bcd2bin(buf[4]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	dt->tm_wday = bcd2bin(buf[5]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	dt->tm_year = (bcd2bin(century) * 100) + bcd2bin(buf[6]) - 1900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static int ds1347_set_time(struct device *dev, struct rtc_time *dt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct regmap *map = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	unsigned int century;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	unsigned char buf[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	err = regmap_update_bits(map, DS1347_STATUS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 				 DS1347_NEOSC_BIT, DS1347_NEOSC_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	buf[0] = bin2bcd(dt->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	buf[1] = bin2bcd(dt->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	buf[2] = (bin2bcd(dt->tm_hour) & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	buf[3] = bin2bcd(dt->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	buf[4] = bin2bcd(dt->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	buf[5] = bin2bcd(dt->tm_wday + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	buf[6] = bin2bcd(dt->tm_year % 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	buf[7] = bin2bcd(0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	err = regmap_bulk_write(map, DS1347_CLOCK_BURST, buf, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	century = (dt->tm_year / 100) + 19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	err = regmap_write(map, DS1347_CENTURY_REG, century);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	return regmap_update_bits(map, DS1347_STATUS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 				  DS1347_NEOSC_BIT | DS1347_OSF_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const struct rtc_class_ops ds1347_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.read_time = ds1347_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.set_time = ds1347_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int ds1347_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	struct regmap_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	memset(&config, 0, sizeof(config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	config.reg_bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	config.val_bits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	config.read_flag_mask = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	config.max_register = 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	config.wr_table = &ds1347_access_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	/* spi setup with ds1347 in mode 3 and bits per word as 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	spi->mode = SPI_MODE_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	spi->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	spi_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	map = devm_regmap_init_spi(spi, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (IS_ERR(map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		dev_err(&spi->dev, "ds1347 regmap init spi failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		return PTR_ERR(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	spi_set_drvdata(spi, map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	/* Disable the write protect of rtc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	err = regmap_update_bits(map, DS1347_CONTROL_REG, DS1347_WP_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	rtc = devm_rtc_allocate_device(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (IS_ERR(rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		return PTR_ERR(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	rtc->ops = &ds1347_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	rtc->range_min = RTC_TIMESTAMP_BEGIN_0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	rtc->range_max = RTC_TIMESTAMP_END_9999;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	return rtc_register_device(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static struct spi_driver ds1347_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		.name = "ds1347",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.probe = ds1347_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) module_spi_driver(ds1347_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MODULE_DESCRIPTION("DS1347 SPI RTC DRIVER");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MODULE_AUTHOR("Raghavendra C Ganiga <ravi23ganiga@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MODULE_LICENSE("GPL v2");