^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* rtc-ds1343.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Driver for Dallas Semiconductor DS1343 Low Current, SPI Compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Real Time Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author : Raghavendra Chandra Ganiga <ravi23ganiga@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Ankur Srivastava <sankurece@gmail.com> : DS1343 Nvram Support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pm_wakeirq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DALLAS_MAXIM_DS1343 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DALLAS_MAXIM_DS1344 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* RTC DS1343 Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DS1343_SECONDS_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DS1343_MINUTES_REG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DS1343_HOURS_REG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DS1343_DAY_REG 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DS1343_DATE_REG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DS1343_MONTH_REG 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DS1343_YEAR_REG 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DS1343_ALM0_SEC_REG 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DS1343_ALM0_MIN_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DS1343_ALM0_HOUR_REG 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DS1343_ALM0_DAY_REG 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DS1343_ALM1_SEC_REG 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DS1343_ALM1_MIN_REG 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DS1343_ALM1_HOUR_REG 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DS1343_ALM1_DAY_REG 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DS1343_CONTROL_REG 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DS1343_STATUS_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DS1343_TRICKLE_REG 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DS1343_NVRAM 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DS1343_NVRAM_LEN 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* DS1343 Control Registers bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DS1343_EOSC 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DS1343_DOSF 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DS1343_EGFIL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DS1343_SQW 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DS1343_INTCN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DS1343_A1IE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DS1343_A0IE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* DS1343 Status Registers bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DS1343_OSF 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DS1343_IRQF1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DS1343_IRQF0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* DS1343 Trickle Charger Registers bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DS1343_TRICKLE_MAGIC 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DS1343_TRICKLE_DS1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DS1343_TRICKLE_1K 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DS1343_TRICKLE_2K 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DS1343_TRICKLE_4K 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const struct spi_device_id ds1343_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { "ds1343", DALLAS_MAXIM_DS1343 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { "ds1344", DALLAS_MAXIM_DS1344 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MODULE_DEVICE_TABLE(spi, ds1343_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct ds1343_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static ssize_t ds1343_show_glitchfilter(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct ds1343_priv *priv = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int glitch_filt_status, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) res = regmap_read(priv->map, DS1343_CONTROL_REG, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) glitch_filt_status = !!(data & DS1343_EGFIL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (glitch_filt_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return sprintf(buf, "enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return sprintf(buf, "disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static ssize_t ds1343_store_glitchfilter(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct ds1343_priv *priv = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (strncmp(buf, "enabled", 7) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) data = DS1343_EGFIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) else if (strncmp(buf, "disabled", 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) res = regmap_update_bits(priv->map, DS1343_CONTROL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) DS1343_EGFIL, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static DEVICE_ATTR(glitch_filter, S_IRUGO | S_IWUSR, ds1343_show_glitchfilter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ds1343_store_glitchfilter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int ds1343_nvram_write(void *priv, unsigned int off, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct ds1343_priv *ds1343 = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return regmap_bulk_write(ds1343->map, DS1343_NVRAM + off, val, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int ds1343_nvram_read(void *priv, unsigned int off, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct ds1343_priv *ds1343 = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return regmap_bulk_read(ds1343->map, DS1343_NVRAM + off, val, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static ssize_t ds1343_show_tricklecharger(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct ds1343_priv *priv = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int res, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) char *diodes = "disabled", *resistors = " ";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) res = regmap_read(priv->map, DS1343_TRICKLE_REG, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if ((data & 0xf0) == DS1343_TRICKLE_MAGIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) switch (data & 0x0c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case DS1343_TRICKLE_DS1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) diodes = "one diode,";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) diodes = "no diode,";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) switch (data & 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) case DS1343_TRICKLE_1K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) resistors = "1k Ohm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case DS1343_TRICKLE_2K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) resistors = "2k Ohm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) case DS1343_TRICKLE_4K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) resistors = "4k Ohm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) diodes = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return sprintf(buf, "%s %s\n", diodes, resistors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static DEVICE_ATTR(trickle_charger, S_IRUGO, ds1343_show_tricklecharger, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct attribute *ds1343_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) &dev_attr_glitch_filter.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) &dev_attr_trickle_charger.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct attribute_group ds1343_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .attrs = ds1343_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int ds1343_read_time(struct device *dev, struct rtc_time *dt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct ds1343_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned char buf[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) res = regmap_bulk_read(priv->map, DS1343_SECONDS_REG, buf, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dt->tm_sec = bcd2bin(buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dt->tm_min = bcd2bin(buf[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dt->tm_hour = bcd2bin(buf[2] & 0x3F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dt->tm_wday = bcd2bin(buf[3]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dt->tm_mday = bcd2bin(buf[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dt->tm_mon = bcd2bin(buf[5] & 0x1F) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dt->tm_year = bcd2bin(buf[6]) + 100; /* year offset from 1900 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int ds1343_set_time(struct device *dev, struct rtc_time *dt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct ds1343_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u8 buf[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) buf[0] = bin2bcd(dt->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) buf[1] = bin2bcd(dt->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) buf[2] = bin2bcd(dt->tm_hour) & 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) buf[3] = bin2bcd(dt->tm_wday + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) buf[4] = bin2bcd(dt->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) buf[5] = bin2bcd(dt->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) buf[6] = bin2bcd(dt->tm_year - 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return regmap_bulk_write(priv->map, DS1343_SECONDS_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int ds1343_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct ds1343_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned char buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (priv->irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) res = regmap_read(priv->map, DS1343_STATUS_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) alarm->pending = !!(val & DS1343_IRQF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) res = regmap_read(priv->map, DS1343_CONTROL_REG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) alarm->enabled = !!(val & DS1343_A0IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) res = regmap_bulk_read(priv->map, DS1343_ALM0_SEC_REG, buf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) alarm->time.tm_sec = bcd2bin(buf[0]) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) alarm->time.tm_min = bcd2bin(buf[1]) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) alarm->time.tm_hour = bcd2bin(buf[2]) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) alarm->time.tm_mday = bcd2bin(buf[3]) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int ds1343_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct ds1343_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned char buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (priv->irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) res = regmap_update_bits(priv->map, DS1343_CONTROL_REG, DS1343_A0IE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) buf[0] = bin2bcd(alarm->time.tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) buf[1] = bin2bcd(alarm->time.tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) buf[2] = bin2bcd(alarm->time.tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) buf[3] = bin2bcd(alarm->time.tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) res = regmap_bulk_write(priv->map, DS1343_ALM0_SEC_REG, buf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (alarm->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) res = regmap_update_bits(priv->map, DS1343_CONTROL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) DS1343_A0IE, DS1343_A0IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int ds1343_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct ds1343_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (priv->irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return regmap_update_bits(priv->map, DS1343_CONTROL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) DS1343_A0IE, enabled ? DS1343_A0IE : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static irqreturn_t ds1343_thread(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct ds1343_priv *priv = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned int stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) rtc_lock(priv->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) res = regmap_read(priv->map, DS1343_STATUS_REG, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (stat & DS1343_IRQF0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) stat &= ~DS1343_IRQF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) regmap_write(priv->map, DS1343_STATUS_REG, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) rtc_update_irq(priv->rtc, 1, RTC_AF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) regmap_update_bits(priv->map, DS1343_CONTROL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) DS1343_A0IE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) rtc_unlock(priv->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const struct rtc_class_ops ds1343_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .read_time = ds1343_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .set_time = ds1343_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .read_alarm = ds1343_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .set_alarm = ds1343_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .alarm_irq_enable = ds1343_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int ds1343_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct ds1343_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct regmap_config config = { .reg_bits = 8, .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .write_flag_mask = 0x80, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct nvmem_config nvmem_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .name = "ds1343-",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .word_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .size = DS1343_NVRAM_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .reg_read = ds1343_nvram_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .reg_write = ds1343_nvram_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) priv = devm_kzalloc(&spi->dev, sizeof(struct ds1343_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* RTC DS1347 works in spi mode 3 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * its chip select is active high. Active high should be defined as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * "inverse polarity" as GPIO-based chip selects can be logically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * active high but inverted by the GPIO library.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) spi->mode |= SPI_MODE_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) spi->mode ^= SPI_CS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) spi->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) res = spi_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) spi_set_drvdata(spi, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) priv->map = devm_regmap_init_spi(spi, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (IS_ERR(priv->map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev_err(&spi->dev, "spi regmap init failed for rtc ds1343\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return PTR_ERR(priv->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) res = regmap_read(priv->map, DS1343_SECONDS_REG, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) regmap_read(priv->map, DS1343_CONTROL_REG, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) data |= DS1343_INTCN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) data &= ~(DS1343_EOSC | DS1343_A1IE | DS1343_A0IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) regmap_write(priv->map, DS1343_CONTROL_REG, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) regmap_read(priv->map, DS1343_STATUS_REG, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) data &= ~(DS1343_OSF | DS1343_IRQF1 | DS1343_IRQF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) regmap_write(priv->map, DS1343_STATUS_REG, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) priv->rtc = devm_rtc_allocate_device(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (IS_ERR(priv->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return PTR_ERR(priv->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) priv->rtc->nvram_old_abi = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) priv->rtc->ops = &ds1343_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) priv->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) priv->rtc->range_max = RTC_TIMESTAMP_END_2099;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) res = rtc_add_group(priv->rtc, &ds1343_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) "unable to create sysfs entries for rtc ds1343\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) res = rtc_register_device(priv->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) nvmem_cfg.priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) rtc_nvmem_register(priv->rtc, &nvmem_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) priv->irq = spi->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (priv->irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) res = devm_request_threaded_irq(&spi->dev, spi->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ds1343_thread, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) "ds1343", priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) priv->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) "unable to request irq for rtc ds1343\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) device_init_wakeup(&spi->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dev_pm_set_wake_irq(&spi->dev, spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int ds1343_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev_pm_clear_wake_irq(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static int ds1343_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (spi->irq >= 0 && device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) enable_irq_wake(spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static int ds1343_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct spi_device *spi = to_spi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (spi->irq >= 0 && device_may_wakeup(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) disable_irq_wake(spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static SIMPLE_DEV_PM_OPS(ds1343_pm, ds1343_suspend, ds1343_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static struct spi_driver ds1343_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .name = "ds1343",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .pm = &ds1343_pm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .probe = ds1343_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .remove = ds1343_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .id_table = ds1343_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) module_spi_driver(ds1343_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MODULE_DESCRIPTION("DS1343 RTC SPI Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MODULE_AUTHOR("Raghavendra Chandra Ganiga <ravi23ganiga@gmail.com>,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) "Ankur Srivastava <sankurece@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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