^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2005 James Chapman (ds1337 core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2006 David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2009 Matthias Fuchs (rx8025 support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2012 Bertrand Achard (nvram access fixes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/rtc/ds1307.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * We can't determine type by probing, but if we expect pre-Linux code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * to have set the chip up as a clock (turning on the oscillator and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * setting the date and time), Linux can ignore the non-clock features.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * That's a natural job for a factory or repair bench.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) enum ds_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ds_1307,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ds_1308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ds_1337,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ds_1338,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ds_1339,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ds_1340,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ds_1341,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ds_1388,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ds_3231,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) m41t0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) m41t00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) m41t11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) mcp794xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) rx_8025,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) rx_8130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) last_ds_type /* always last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* rs5c372 too? different address... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* RTC registers don't differ much, except for the century flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DS1307_REG_SECS 0x00 /* 00-59 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) # define DS1307_BIT_CH 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) # define DS1340_BIT_nEOSC 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) # define MCP794XX_BIT_ST 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DS1307_REG_MIN 0x01 /* 00-59 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) # define M41T0_BIT_OF 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) # define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) # define DS1307_BIT_PM 0x20 /* in REG_HOUR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) # define DS1340_BIT_CENTURY_EN 0x80 /* in REG_HOUR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) # define DS1340_BIT_CENTURY 0x40 /* in REG_HOUR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DS1307_REG_WDAY 0x03 /* 01-07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) # define MCP794XX_BIT_VBATEN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DS1307_REG_MDAY 0x04 /* 01-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DS1307_REG_MONTH 0x05 /* 01-12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) # define DS1337_BIT_CENTURY 0x80 /* in REG_MONTH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DS1307_REG_YEAR 0x06 /* 00-99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * Other registers (control, status, alarms, trickle charge, NVRAM, etc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * start at 7, and they differ a LOT. Only control and status matter for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * basic RTC date and time functionality; be careful using them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DS1307_REG_CONTROL 0x07 /* or ds1338 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) # define DS1307_BIT_OUT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) # define DS1338_BIT_OSF 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) # define DS1307_BIT_SQWE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) # define DS1307_BIT_RS1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) # define DS1307_BIT_RS0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DS1337_REG_CONTROL 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) # define DS1337_BIT_nEOSC 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) # define DS1339_BIT_BBSQI 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) # define DS3231_BIT_BBSQW 0x40 /* same as BBSQI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) # define DS1337_BIT_RS2 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) # define DS1337_BIT_RS1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) # define DS1337_BIT_INTCN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) # define DS1337_BIT_A2IE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) # define DS1337_BIT_A1IE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DS1340_REG_CONTROL 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) # define DS1340_BIT_OUT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) # define DS1340_BIT_FT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) # define DS1340_BIT_CALIB_SIGN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) # define DS1340_M_CALIBRATION 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DS1340_REG_FLAG 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) # define DS1340_BIT_OSF 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DS1337_REG_STATUS 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) # define DS1337_BIT_OSF 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) # define DS3231_BIT_EN32KHZ 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) # define DS1337_BIT_A2I 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) # define DS1337_BIT_A1I 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DS1339_REG_ALARM1_SECS 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DS13XX_TRICKLE_CHARGER_MAGIC 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RX8025_REG_CTRL1 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) # define RX8025_BIT_2412 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RX8025_REG_CTRL2 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) # define RX8025_BIT_PON 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) # define RX8025_BIT_VDET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) # define RX8025_BIT_XST 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RX8130_REG_ALARM_MIN 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define RX8130_REG_ALARM_HOUR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define RX8130_REG_ALARM_WEEK_OR_DAY 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RX8130_REG_EXTENSION 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RX8130_REG_EXTENSION_WADA BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RX8130_REG_FLAG 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RX8130_REG_FLAG_VLF BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RX8130_REG_FLAG_AF BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define RX8130_REG_CONTROL0 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RX8130_REG_CONTROL0_AIE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RX8130_REG_CONTROL1 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RX8130_REG_CONTROL1_INIEN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RX8130_REG_CONTROL1_CHGEN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MCP794XX_REG_CONTROL 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) # define MCP794XX_BIT_ALM0_EN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) # define MCP794XX_BIT_ALM1_EN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MCP794XX_REG_ALARM0_BASE 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MCP794XX_REG_ALARM0_CTRL 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MCP794XX_REG_ALARM1_BASE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MCP794XX_REG_ALARM1_CTRL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) # define MCP794XX_BIT_ALMX_IF BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) # define MCP794XX_BIT_ALMX_C0 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) # define MCP794XX_BIT_ALMX_C1 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) # define MCP794XX_BIT_ALMX_C2 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) # define MCP794XX_BIT_ALMX_POL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) # define MCP794XX_MSK_ALMX_MATCH (MCP794XX_BIT_ALMX_C0 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MCP794XX_BIT_ALMX_C1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MCP794XX_BIT_ALMX_C2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define M41TXX_REG_CONTROL 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) # define M41TXX_BIT_OUT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) # define M41TXX_BIT_FT BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) # define M41TXX_BIT_CALIB_SIGN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) # define M41TXX_M_CALIBRATION GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DS1388_REG_WDOG_HUN_SECS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DS1388_REG_WDOG_SECS 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DS1388_REG_FLAG 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) # define DS1388_BIT_WF BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) # define DS1388_BIT_OSF BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DS1388_REG_CONTROL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) # define DS1388_BIT_RST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) # define DS1388_BIT_WDE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) # define DS1388_BIT_nEOSC BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* negative offset step is -2.034ppm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define M41TXX_NEG_OFFSET_STEP_PPB 2034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* positive offset step is +4.068ppm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define M41TXX_POS_OFFSET_STEP_PPB 4068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Min and max values supported with 'offset' interface by M41TXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define M41TXX_MIN_OFFSET ((-31) * M41TXX_NEG_OFFSET_STEP_PPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define M41TXX_MAX_OFFSET ((31) * M41TXX_POS_OFFSET_STEP_PPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct ds1307 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) enum ds_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define HAS_NVRAM 0 /* bit 0 == sysfs file active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define HAS_ALARM 1 /* bit 1 == irq claimed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #ifdef CONFIG_COMMON_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct clk_hw clks[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct chip_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned alarm:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u16 nvram_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u16 nvram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u8 offset; /* register's offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u8 century_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u8 century_enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u8 century_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u8 bbsqi_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) irq_handler_t irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) const struct rtc_class_ops *rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u16 trickle_charger_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u8 (*do_trickle_setup)(struct ds1307 *, u32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) bool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Does the RTC require trickle-resistor-ohms to select the value of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * the resistor between Vcc and Vbackup?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) bool requires_trickle_resistor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Some RTC's batteries and supercaps were charged by default, others
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * allow charging but were not configured previously to do so.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * Remember this behavior to stay backwards compatible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) bool charge_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const struct chip_desc chips[last_ds_type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int ds1307_get_time(struct device *dev, struct rtc_time *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct ds1307 *ds1307 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int tmp, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) const struct chip_desc *chip = &chips[ds1307->type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u8 regs[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (ds1307->type == rx_8130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned int regflag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ret = regmap_read(ds1307->regmap, RX8130_REG_FLAG, ®flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dev_err(dev, "%s error %d\n", "read", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (regflag & RX8130_REG_FLAG_VLF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dev_warn_once(dev, "oscillator failed, set time!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* read the RTC date and time registers all at once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ret = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) sizeof(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev_err(dev, "%s error %d\n", "read", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_dbg(dev, "%s: %7ph\n", "read", regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* if oscillator fail bit is set, no data can be trusted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (ds1307->type == m41t0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev_warn_once(dev, "oscillator failed, set time!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) tmp = regs[DS1307_REG_SECS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) switch (ds1307->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case ds_1307:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) case m41t0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case m41t00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) case m41t11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (tmp & DS1307_BIT_CH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case ds_1308:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case ds_1338:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (tmp & DS1307_BIT_CH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret = regmap_read(ds1307->regmap, DS1307_REG_CONTROL, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (tmp & DS1338_BIT_OSF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case ds_1340:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (tmp & DS1340_BIT_nEOSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ret = regmap_read(ds1307->regmap, DS1340_REG_FLAG, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (tmp & DS1340_BIT_OSF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) case ds_1388:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ret = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (tmp & DS1388_BIT_OSF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case mcp794xx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (!(tmp & MCP794XX_BIT_ST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) t->tm_sec = bcd2bin(regs[DS1307_REG_SECS] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) t->tm_min = bcd2bin(regs[DS1307_REG_MIN] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) tmp = regs[DS1307_REG_HOUR] & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) t->tm_hour = bcd2bin(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* rx8130 is bit position, not BCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (ds1307->type == rx_8130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) t->tm_wday = fls(regs[DS1307_REG_WDAY] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) t->tm_wday = bcd2bin(regs[DS1307_REG_WDAY] & 0x07) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) t->tm_mday = bcd2bin(regs[DS1307_REG_MDAY] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) tmp = regs[DS1307_REG_MONTH] & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) t->tm_mon = bcd2bin(tmp) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) t->tm_year = bcd2bin(regs[DS1307_REG_YEAR]) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (regs[chip->century_reg] & chip->century_bit &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) IS_ENABLED(CONFIG_RTC_DRV_DS1307_CENTURY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) t->tm_year += 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev_dbg(dev, "%s secs=%d, mins=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) "read", t->tm_sec, t->tm_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) t->tm_hour, t->tm_mday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) t->tm_mon, t->tm_year, t->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int ds1307_set_time(struct device *dev, struct rtc_time *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct ds1307 *ds1307 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) const struct chip_desc *chip = &chips[ds1307->type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u8 regs[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dev_dbg(dev, "%s secs=%d, mins=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "write", t->tm_sec, t->tm_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) t->tm_hour, t->tm_mday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) t->tm_mon, t->tm_year, t->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (t->tm_year < 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #ifdef CONFIG_RTC_DRV_DS1307_CENTURY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (t->tm_year > (chip->century_bit ? 299 : 199))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (t->tm_year > 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) regs[DS1307_REG_SECS] = bin2bcd(t->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) regs[DS1307_REG_MIN] = bin2bcd(t->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) regs[DS1307_REG_HOUR] = bin2bcd(t->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* rx8130 is bit position, not BCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (ds1307->type == rx_8130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) regs[DS1307_REG_WDAY] = 1 << t->tm_wday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) regs[DS1307_REG_WDAY] = bin2bcd(t->tm_wday + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) regs[DS1307_REG_MDAY] = bin2bcd(t->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) regs[DS1307_REG_MONTH] = bin2bcd(t->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* assume 20YY not 19YY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) tmp = t->tm_year - 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) regs[DS1307_REG_YEAR] = bin2bcd(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (chip->century_enable_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) regs[chip->century_reg] |= chip->century_enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (t->tm_year > 199 && chip->century_bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) regs[chip->century_reg] |= chip->century_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) switch (ds1307->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) case ds_1308:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) case ds_1338:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) regmap_update_bits(ds1307->regmap, DS1307_REG_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) DS1338_BIT_OSF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) case ds_1340:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) regmap_update_bits(ds1307->regmap, DS1340_REG_FLAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) DS1340_BIT_OSF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) case ds_1388:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) DS1388_BIT_OSF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) case mcp794xx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * these bits were cleared when preparing the date/time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * values and need to be set again before writing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * regsfer out to the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) regs[DS1307_REG_SECS] |= MCP794XX_BIT_ST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) regs[DS1307_REG_WDAY] |= MCP794XX_BIT_VBATEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_dbg(dev, "%s: %7ph\n", "write", regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) result = regmap_bulk_write(ds1307->regmap, chip->offset, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) sizeof(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev_err(dev, "%s error %d\n", "write", result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (ds1307->type == rx_8130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* clear Voltage Loss Flag as data is available now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) result = regmap_write(ds1307->regmap, RX8130_REG_FLAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ~(u8)RX8130_REG_FLAG_VLF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dev_err(dev, "%s error %d\n", "write", result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct ds1307 *ds1307 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u8 regs[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (!test_bit(HAS_ALARM, &ds1307->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* read all ALARM1, ALARM2, and status registers at once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) regs, sizeof(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev_err(dev, "%s error %d\n", "alarm read", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dev_dbg(dev, "%s: %4ph, %3ph, %2ph\n", "alarm read",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ®s[0], ®s[4], ®s[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * report alarm time (ALARM1); assume 24 hour and day-of-month modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * and that all four fields are checked matches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) t->time.tm_sec = bcd2bin(regs[0] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) t->time.tm_min = bcd2bin(regs[1] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) t->time.tm_hour = bcd2bin(regs[2] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) t->time.tm_mday = bcd2bin(regs[3] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* ... and status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) t->enabled = !!(regs[7] & DS1337_BIT_A1IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) t->pending = !!(regs[8] & DS1337_BIT_A1I);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dev_dbg(dev, "%s secs=%d, mins=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) "hours=%d, mday=%d, enabled=%d, pending=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) "alarm read", t->time.tm_sec, t->time.tm_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) t->time.tm_hour, t->time.tm_mday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) t->enabled, t->pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct ds1307 *ds1307 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned char regs[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u8 control, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (!test_bit(HAS_ALARM, &ds1307->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dev_dbg(dev, "%s secs=%d, mins=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) "hours=%d, mday=%d, enabled=%d, pending=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "alarm set", t->time.tm_sec, t->time.tm_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) t->time.tm_hour, t->time.tm_mday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) t->enabled, t->pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* read current status of both alarms and the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ret = regmap_bulk_read(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) sizeof(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_err(dev, "%s error %d\n", "alarm write", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) control = regs[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) status = regs[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dev_dbg(dev, "%s: %4ph, %3ph, %02x %02x\n", "alarm set (old status)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ®s[0], ®s[4], control, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* set ALARM1, using 24 hour and day-of-month modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) regs[0] = bin2bcd(t->time.tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) regs[1] = bin2bcd(t->time.tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) regs[2] = bin2bcd(t->time.tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) regs[3] = bin2bcd(t->time.tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* set ALARM2 to non-garbage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) regs[4] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) regs[5] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) regs[6] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* disable alarms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) regs[7] = control & ~(DS1337_BIT_A1IE | DS1337_BIT_A2IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) regs[8] = status & ~(DS1337_BIT_A1I | DS1337_BIT_A2I);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ret = regmap_bulk_write(ds1307->regmap, DS1339_REG_ALARM1_SECS, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) sizeof(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dev_err(dev, "can't set alarm time\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* optionally enable ALARM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (t->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dev_dbg(dev, "alarm IRQ armed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) regs[7] |= DS1337_BIT_A1IE; /* only ALARM1 is used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) regmap_write(ds1307->regmap, DS1337_REG_CONTROL, regs[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct ds1307 *ds1307 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (!test_bit(HAS_ALARM, &ds1307->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) DS1337_BIT_A1IE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) enabled ? DS1337_BIT_A1IE : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u8 setup = (diode) ? DS1307_TRICKLE_CHARGER_DIODE :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) DS1307_TRICKLE_CHARGER_NO_DIODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) setup |= DS13XX_TRICKLE_CHARGER_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) switch (ohms) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) case 250:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) setup |= DS1307_TRICKLE_CHARGER_250_OHM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) case 2000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) setup |= DS1307_TRICKLE_CHARGER_2K_OHM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) case 4000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) setup |= DS1307_TRICKLE_CHARGER_4K_OHM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) dev_warn(ds1307->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) "Unsupported ohm value %u in dt\n", ohms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static u8 do_trickle_setup_rx8130(struct ds1307 *ds1307, u32 ohms, bool diode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* make sure that the backup battery is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u8 setup = RX8130_REG_CONTROL1_INIEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (diode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) setup |= RX8130_REG_CONTROL1_CHGEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static irqreturn_t rx8130_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct ds1307 *ds1307 = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct mutex *lock = &ds1307->rtc->ops_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u8 ctl[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) mutex_lock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* Read control registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) sizeof(ctl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (!(ctl[1] & RX8130_REG_FLAG_AF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ctl[1] &= ~RX8130_REG_FLAG_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) sizeof(ctl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) mutex_unlock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct ds1307 *ds1307 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) u8 ald[3], ctl[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (!test_bit(HAS_ALARM, &ds1307->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* Read alarm registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) sizeof(ald));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* Read control registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) sizeof(ctl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) t->enabled = !!(ctl[2] & RX8130_REG_CONTROL0_AIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) t->pending = !!(ctl[1] & RX8130_REG_FLAG_AF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) t->time.tm_sec = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) t->time.tm_min = bcd2bin(ald[0] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) t->time.tm_hour = bcd2bin(ald[1] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) t->time.tm_wday = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) t->time.tm_mday = bcd2bin(ald[2] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) t->time.tm_mon = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) t->time.tm_year = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) t->time.tm_yday = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) t->time.tm_isdst = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d enabled=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) __func__, t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct ds1307 *ds1307 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u8 ald[3], ctl[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (!test_bit(HAS_ALARM, &ds1307->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) "enabled=%d pending=%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) t->enabled, t->pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* Read control registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ret = regmap_bulk_read(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) sizeof(ctl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ctl[0] &= RX8130_REG_EXTENSION_WADA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ctl[1] &= ~RX8130_REG_FLAG_AF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ctl[2] &= ~RX8130_REG_CONTROL0_AIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_EXTENSION, ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) sizeof(ctl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* Hardware alarm precision is 1 minute! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ald[0] = bin2bcd(t->time.tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ald[1] = bin2bcd(t->time.tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ald[2] = bin2bcd(t->time.tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ret = regmap_bulk_write(ds1307->regmap, RX8130_REG_ALARM_MIN, ald,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) sizeof(ald));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (!t->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ctl[2] |= RX8130_REG_CONTROL0_AIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, ctl[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct ds1307 *ds1307 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int ret, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (!test_bit(HAS_ALARM, &ds1307->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ret = regmap_read(ds1307->regmap, RX8130_REG_CONTROL0, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) reg |= RX8130_REG_CONTROL0_AIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) reg &= ~RX8130_REG_CONTROL0_AIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return regmap_write(ds1307->regmap, RX8130_REG_CONTROL0, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static irqreturn_t mcp794xx_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct ds1307 *ds1307 = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct mutex *lock = &ds1307->rtc->ops_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) int reg, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) mutex_lock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* Check and clear alarm 0 interrupt flag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ret = regmap_read(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (!(reg & MCP794XX_BIT_ALMX_IF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) reg &= ~MCP794XX_BIT_ALMX_IF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ret = regmap_write(ds1307->regmap, MCP794XX_REG_ALARM0_CTRL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* Disable alarm 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ret = regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) MCP794XX_BIT_ALM0_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) mutex_unlock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct ds1307 *ds1307 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) u8 regs[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (!test_bit(HAS_ALARM, &ds1307->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* Read control and alarm 0 registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) sizeof(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) t->enabled = !!(regs[0] & MCP794XX_BIT_ALM0_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* Report alarm 0 time assuming 24-hour and day-of-month modes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) t->time.tm_sec = bcd2bin(regs[3] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) t->time.tm_min = bcd2bin(regs[4] & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) t->time.tm_hour = bcd2bin(regs[5] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) t->time.tm_wday = bcd2bin(regs[6] & 0x7) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) t->time.tm_mday = bcd2bin(regs[7] & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) t->time.tm_mon = bcd2bin(regs[8] & 0x1f) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) t->time.tm_year = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) t->time.tm_yday = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) t->time.tm_isdst = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) "enabled=%d polarity=%d irq=%d match=%lu\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) t->time.tm_wday, t->time.tm_mday, t->time.tm_mon, t->enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) !!(regs[6] & MCP794XX_BIT_ALMX_POL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) !!(regs[6] & MCP794XX_BIT_ALMX_IF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) (regs[6] & MCP794XX_MSK_ALMX_MATCH) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * We may have a random RTC weekday, therefore calculate alarm weekday based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * on current weekday we read from the RTC timekeeping regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct rtc_time tm_now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) int days_now, days_alarm, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ret = ds1307_get_time(dev, &tm_now);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) days_now = div_s64(rtc_tm_to_time64(&tm_now), 24 * 60 * 60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) days_alarm = div_s64(rtc_tm_to_time64(tm_alarm), 24 * 60 * 60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return (tm_now.tm_wday + days_alarm - days_now) % 7 + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct ds1307 *ds1307 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) unsigned char regs[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) int wday, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (!test_bit(HAS_ALARM, &ds1307->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) wday = mcp794xx_alm_weekday(dev, &t->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (wday < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return wday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) dev_dbg(dev, "%s, sec=%d min=%d hour=%d wday=%d mday=%d mon=%d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) "enabled=%d pending=%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) t->time.tm_sec, t->time.tm_min, t->time.tm_hour,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) t->time.tm_wday, t->time.tm_mday, t->time.tm_mon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) t->enabled, t->pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* Read control and alarm 0 registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ret = regmap_bulk_read(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) sizeof(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* Set alarm 0, using 24-hour and day-of-month modes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) regs[3] = bin2bcd(t->time.tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) regs[4] = bin2bcd(t->time.tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) regs[5] = bin2bcd(t->time.tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) regs[6] = wday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) regs[7] = bin2bcd(t->time.tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) regs[8] = bin2bcd(t->time.tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /* Clear the alarm 0 interrupt flag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) regs[6] &= ~MCP794XX_BIT_ALMX_IF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* Set alarm match: second, minute, hour, day, date, month. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) regs[6] |= MCP794XX_MSK_ALMX_MATCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* Disable interrupt. We will not enable until completely programmed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) regs[0] &= ~MCP794XX_BIT_ALM0_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ret = regmap_bulk_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) sizeof(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (!t->enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) regs[0] |= MCP794XX_BIT_ALM0_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return regmap_write(ds1307->regmap, MCP794XX_REG_CONTROL, regs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct ds1307 *ds1307 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (!test_bit(HAS_ALARM, &ds1307->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return regmap_update_bits(ds1307->regmap, MCP794XX_REG_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) MCP794XX_BIT_ALM0_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) enabled ? MCP794XX_BIT_ALM0_EN : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static int m41txx_rtc_read_offset(struct device *dev, long *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct ds1307 *ds1307 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) unsigned int ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) val = ctrl_reg & M41TXX_M_CALIBRATION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* check if positive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (ctrl_reg & M41TXX_BIT_CALIB_SIGN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) *offset = (val * M41TXX_POS_OFFSET_STEP_PPB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) *offset = -(val * M41TXX_NEG_OFFSET_STEP_PPB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static int m41txx_rtc_set_offset(struct device *dev, long offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct ds1307 *ds1307 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) unsigned int ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if ((offset < M41TXX_MIN_OFFSET) || (offset > M41TXX_MAX_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (offset >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) ctrl_reg = DIV_ROUND_CLOSEST(offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) M41TXX_POS_OFFSET_STEP_PPB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ctrl_reg |= M41TXX_BIT_CALIB_SIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) ctrl_reg = DIV_ROUND_CLOSEST(abs(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) M41TXX_NEG_OFFSET_STEP_PPB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) M41TXX_M_CALIBRATION | M41TXX_BIT_CALIB_SIGN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #ifdef CONFIG_WATCHDOG_CORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static int ds1388_wdt_start(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) u8 regs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) ret = regmap_update_bits(ds1307->regmap, DS1388_REG_FLAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) DS1388_BIT_WF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ret = regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) DS1388_BIT_WDE | DS1388_BIT_RST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * watchdog timeouts are measured in seconds. So ignore hundredths of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * seconds field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) regs[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) regs[1] = bin2bcd(wdt_dev->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) ret = regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) sizeof(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) DS1388_BIT_WDE | DS1388_BIT_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) DS1388_BIT_WDE | DS1388_BIT_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static int ds1388_wdt_stop(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return regmap_update_bits(ds1307->regmap, DS1388_REG_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) DS1388_BIT_WDE | DS1388_BIT_RST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static int ds1388_wdt_ping(struct watchdog_device *wdt_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) u8 regs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return regmap_bulk_read(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) sizeof(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static int ds1388_wdt_set_timeout(struct watchdog_device *wdt_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) struct ds1307 *ds1307 = watchdog_get_drvdata(wdt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) u8 regs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) wdt_dev->timeout = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) regs[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) regs[1] = bin2bcd(wdt_dev->timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return regmap_bulk_write(ds1307->regmap, DS1388_REG_WDOG_HUN_SECS, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) sizeof(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static const struct rtc_class_ops rx8130_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .read_time = ds1307_get_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .set_time = ds1307_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .read_alarm = rx8130_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .set_alarm = rx8130_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .alarm_irq_enable = rx8130_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static const struct rtc_class_ops mcp794xx_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .read_time = ds1307_get_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .set_time = ds1307_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .read_alarm = mcp794xx_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .set_alarm = mcp794xx_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .alarm_irq_enable = mcp794xx_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static const struct rtc_class_ops m41txx_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .read_time = ds1307_get_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .set_time = ds1307_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .read_alarm = ds1337_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .set_alarm = ds1337_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .alarm_irq_enable = ds1307_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .read_offset = m41txx_rtc_read_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .set_offset = m41txx_rtc_set_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static const struct chip_desc chips[last_ds_type] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) [ds_1307] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .nvram_offset = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .nvram_size = 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) [ds_1308] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .nvram_offset = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .nvram_size = 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) [ds_1337] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .alarm = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .century_reg = DS1307_REG_MONTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .century_bit = DS1337_BIT_CENTURY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) [ds_1338] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .nvram_offset = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .nvram_size = 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) [ds_1339] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .alarm = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .century_reg = DS1307_REG_MONTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .century_bit = DS1337_BIT_CENTURY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .bbsqi_bit = DS1339_BIT_BBSQI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .trickle_charger_reg = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .do_trickle_setup = &do_trickle_setup_ds1339,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .requires_trickle_resistor = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .charge_default = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) [ds_1340] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .century_reg = DS1307_REG_HOUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .century_enable_bit = DS1340_BIT_CENTURY_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .century_bit = DS1340_BIT_CENTURY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .do_trickle_setup = &do_trickle_setup_ds1339,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .trickle_charger_reg = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .requires_trickle_resistor = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .charge_default = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) [ds_1341] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .century_reg = DS1307_REG_MONTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .century_bit = DS1337_BIT_CENTURY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) [ds_1388] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .offset = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .trickle_charger_reg = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) [ds_3231] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .alarm = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .century_reg = DS1307_REG_MONTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .century_bit = DS1337_BIT_CENTURY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .bbsqi_bit = DS3231_BIT_BBSQW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) [rx_8130] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .alarm = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /* this is battery backed SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .nvram_offset = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .nvram_size = 4, /* 32bit (4 word x 8 bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .offset = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .irq_handler = rx8130_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .rtc_ops = &rx8130_rtc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .trickle_charger_reg = RX8130_REG_CONTROL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .do_trickle_setup = &do_trickle_setup_rx8130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) [m41t0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .rtc_ops = &m41txx_rtc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) [m41t00] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .rtc_ops = &m41txx_rtc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) [m41t11] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* this is battery backed SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .nvram_offset = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .nvram_size = 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .rtc_ops = &m41txx_rtc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) [mcp794xx] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .alarm = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /* this is battery backed SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .nvram_offset = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .nvram_size = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .irq_handler = mcp794xx_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .rtc_ops = &mcp794xx_rtc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static const struct i2c_device_id ds1307_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) { "ds1307", ds_1307 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) { "ds1308", ds_1308 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) { "ds1337", ds_1337 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) { "ds1338", ds_1338 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) { "ds1339", ds_1339 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) { "ds1388", ds_1388 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) { "ds1340", ds_1340 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) { "ds1341", ds_1341 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) { "ds3231", ds_3231 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) { "m41t0", m41t0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) { "m41t00", m41t00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) { "m41t11", m41t11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) { "mcp7940x", mcp794xx },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) { "mcp7941x", mcp794xx },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) { "pt7c4338", ds_1307 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) { "rx8025", rx_8025 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) { "isl12057", ds_1337 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) { "rx8130", rx_8130 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) MODULE_DEVICE_TABLE(i2c, ds1307_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) static const struct of_device_id ds1307_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .compatible = "dallas,ds1307",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .data = (void *)ds_1307
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .compatible = "dallas,ds1308",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .data = (void *)ds_1308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .compatible = "dallas,ds1337",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .data = (void *)ds_1337
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .compatible = "dallas,ds1338",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .data = (void *)ds_1338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .compatible = "dallas,ds1339",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .data = (void *)ds_1339
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .compatible = "dallas,ds1388",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .data = (void *)ds_1388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .compatible = "dallas,ds1340",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .data = (void *)ds_1340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .compatible = "dallas,ds1341",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .data = (void *)ds_1341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .compatible = "maxim,ds3231",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .data = (void *)ds_3231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .compatible = "st,m41t0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .data = (void *)m41t0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .compatible = "st,m41t00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .data = (void *)m41t00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .compatible = "st,m41t11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .data = (void *)m41t11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .compatible = "microchip,mcp7940x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .data = (void *)mcp794xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .compatible = "microchip,mcp7941x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .data = (void *)mcp794xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .compatible = "pericom,pt7c4338",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .data = (void *)ds_1307
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .compatible = "epson,rx8025",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .data = (void *)rx_8025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .compatible = "isil,isl12057",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .data = (void *)ds_1337
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .compatible = "epson,rx8130",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .data = (void *)rx_8130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) MODULE_DEVICE_TABLE(of, ds1307_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) static const struct acpi_device_id ds1307_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) { .id = "DS1307", .driver_data = ds_1307 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) { .id = "DS1308", .driver_data = ds_1308 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) { .id = "DS1337", .driver_data = ds_1337 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) { .id = "DS1338", .driver_data = ds_1338 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) { .id = "DS1339", .driver_data = ds_1339 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) { .id = "DS1388", .driver_data = ds_1388 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) { .id = "DS1340", .driver_data = ds_1340 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) { .id = "DS1341", .driver_data = ds_1341 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) { .id = "DS3231", .driver_data = ds_3231 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) { .id = "M41T0", .driver_data = m41t0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) { .id = "M41T00", .driver_data = m41t00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) { .id = "M41T11", .driver_data = m41t11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) { .id = "MCP7940X", .driver_data = mcp794xx },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) { .id = "MCP7941X", .driver_data = mcp794xx },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) { .id = "PT7C4338", .driver_data = ds_1307 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) { .id = "RX8025", .driver_data = rx_8025 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) { .id = "ISL12057", .driver_data = ds_1337 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) { .id = "RX8130", .driver_data = rx_8130 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * The ds1337 and ds1339 both have two alarms, but we only use the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * signal; ds1339 chips have only one alarm signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static irqreturn_t ds1307_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) struct ds1307 *ds1307 = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct mutex *lock = &ds1307->rtc->ops_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) int stat, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) mutex_lock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (stat & DS1337_BIT_A1I) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) stat &= ~DS1337_BIT_A1I;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) regmap_write(ds1307->regmap, DS1337_REG_STATUS, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) DS1337_BIT_A1IE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) rtc_update_irq(ds1307->rtc, 1, RTC_AF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) mutex_unlock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) static const struct rtc_class_ops ds13xx_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .read_time = ds1307_get_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .set_time = ds1307_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .read_alarm = ds1337_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .set_alarm = ds1337_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .alarm_irq_enable = ds1307_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) static ssize_t frequency_test_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) bool freq_test_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) ret = kstrtobool(buf, &freq_test_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) dev_err(dev, "Failed to store RTC Frequency Test attribute\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) regmap_update_bits(ds1307->regmap, M41TXX_REG_CONTROL, M41TXX_BIT_FT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) freq_test_en ? M41TXX_BIT_FT : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static ssize_t frequency_test_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) struct ds1307 *ds1307 = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) unsigned int ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) regmap_read(ds1307->regmap, M41TXX_REG_CONTROL, &ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) return scnprintf(buf, PAGE_SIZE, (ctrl_reg & M41TXX_BIT_FT) ? "on\n" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) "off\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) static DEVICE_ATTR_RW(frequency_test);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static struct attribute *rtc_freq_test_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) &dev_attr_frequency_test.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) static const struct attribute_group rtc_freq_test_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .attrs = rtc_freq_test_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) static int ds1307_add_frequency_test(struct ds1307 *ds1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) switch (ds1307->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) case m41t0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) case m41t00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) case m41t11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) err = rtc_add_group(ds1307->rtc, &rtc_freq_test_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) static int ds1307_nvram_read(void *priv, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) struct ds1307 *ds1307 = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) const struct chip_desc *chip = &chips[ds1307->type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) return regmap_bulk_read(ds1307->regmap, chip->nvram_offset + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) val, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) static int ds1307_nvram_write(void *priv, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) struct ds1307 *ds1307 = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) const struct chip_desc *chip = &chips[ds1307->type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return regmap_bulk_write(ds1307->regmap, chip->nvram_offset + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) val, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) static u8 ds1307_trickle_init(struct ds1307 *ds1307,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) const struct chip_desc *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) u32 ohms, chargeable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) bool diode = chip->charge_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (!chip->do_trickle_setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (device_property_read_u32(ds1307->dev, "trickle-resistor-ohms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) &ohms) && chip->requires_trickle_resistor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) /* aux-voltage-chargeable takes precedence over the deprecated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) * trickle-diode-disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (!device_property_read_u32(ds1307->dev, "aux-voltage-chargeable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) &chargeable)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) switch (chargeable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) diode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) diode = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) dev_warn(ds1307->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) "unsupported aux-voltage-chargeable value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) } else if (device_property_read_bool(ds1307->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) "trickle-diode-disable")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) diode = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return chip->do_trickle_setup(ds1307, ohms, diode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) #if IS_REACHABLE(CONFIG_HWMON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) * Temperature sensor support for ds3231 devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) #define DS3231_REG_TEMPERATURE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) * A user-initiated temperature conversion is not started by this function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) * so the temperature is updated once every 64 seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) struct ds1307 *ds1307 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) u8 temp_buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) s16 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) ret = regmap_bulk_read(ds1307->regmap, DS3231_REG_TEMPERATURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) temp_buf, sizeof(temp_buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * Temperature is represented as a 10-bit code with a resolution of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) * 0.25 degree celsius and encoded in two's complement format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) temp = (temp_buf[0] << 8) | temp_buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) temp >>= 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) *mC = temp * 250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) static ssize_t ds3231_hwmon_show_temp(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) s32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) ret = ds3231_hwmon_read_temp(dev, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) return sprintf(buf, "%d\n", temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) static struct attribute *ds3231_hwmon_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) &sensor_dev_attr_temp1_input.dev_attr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) ATTRIBUTE_GROUPS(ds3231_hwmon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static void ds1307_hwmon_register(struct ds1307 *ds1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (ds1307->type != ds_3231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) dev = devm_hwmon_device_register_with_groups(ds1307->dev, ds1307->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) ds1307,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) ds3231_hwmon_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) if (IS_ERR(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) dev_warn(ds1307->dev, "unable to register hwmon device %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) PTR_ERR(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) static void ds1307_hwmon_register(struct ds1307 *ds1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #endif /* CONFIG_RTC_DRV_DS1307_HWMON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) * Square-wave output support for DS3231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) #ifdef CONFIG_COMMON_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) DS3231_CLK_SQW = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) DS3231_CLK_32KHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) #define clk_sqw_to_ds1307(clk) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) container_of(clk, struct ds1307, clks[DS3231_CLK_SQW])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) #define clk_32khz_to_ds1307(clk) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) container_of(clk, struct ds1307, clks[DS3231_CLK_32KHZ])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static int ds3231_clk_sqw_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) 4096,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) 8192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) struct mutex *lock = &ds1307->rtc->ops_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) mutex_lock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) ret = regmap_update_bits(ds1307->regmap, DS1337_REG_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) mutex_unlock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) int control, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) int rate_sel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if (control & DS1337_BIT_RS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) rate_sel += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) if (control & DS1337_BIT_RS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) rate_sel += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) return ds3231_clk_sqw_rates[rate_sel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) for (i = ARRAY_SIZE(ds3231_clk_sqw_rates) - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) if (ds3231_clk_sqw_rates[i] <= rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) return ds3231_clk_sqw_rates[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) int control = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) int rate_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) for (rate_sel = 0; rate_sel < ARRAY_SIZE(ds3231_clk_sqw_rates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) rate_sel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) if (ds3231_clk_sqw_rates[rate_sel] == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if (rate_sel == ARRAY_SIZE(ds3231_clk_sqw_rates))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) if (rate_sel & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) control |= DS1337_BIT_RS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) if (rate_sel & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) control |= DS1337_BIT_RS2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) return ds1337_write_control(ds1307, DS1337_BIT_RS1 | DS1337_BIT_RS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) static int ds3231_clk_sqw_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) return ds1337_write_control(ds1307, DS1337_BIT_INTCN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) static void ds3231_clk_sqw_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) ds1337_write_control(ds1307, DS1337_BIT_INTCN, DS1337_BIT_INTCN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) struct ds1307 *ds1307 = clk_sqw_to_ds1307(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) int control, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) ret = regmap_read(ds1307->regmap, DS1337_REG_CONTROL, &control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) return !(control & DS1337_BIT_INTCN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static const struct clk_ops ds3231_clk_sqw_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .prepare = ds3231_clk_sqw_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .unprepare = ds3231_clk_sqw_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .is_prepared = ds3231_clk_sqw_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .recalc_rate = ds3231_clk_sqw_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .round_rate = ds3231_clk_sqw_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .set_rate = ds3231_clk_sqw_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) return 32768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) struct mutex *lock = &ds1307->rtc->ops_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) mutex_lock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) ret = regmap_update_bits(ds1307->regmap, DS1337_REG_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) DS3231_BIT_EN32KHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) enable ? DS3231_BIT_EN32KHZ : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) mutex_unlock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) static int ds3231_clk_32khz_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) return ds3231_clk_32khz_control(ds1307, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) static void ds3231_clk_32khz_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) ds3231_clk_32khz_control(ds1307, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) struct ds1307 *ds1307 = clk_32khz_to_ds1307(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) int status, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) ret = regmap_read(ds1307->regmap, DS1337_REG_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) return !!(status & DS3231_BIT_EN32KHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) static const struct clk_ops ds3231_clk_32khz_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .prepare = ds3231_clk_32khz_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .unprepare = ds3231_clk_32khz_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .is_prepared = ds3231_clk_32khz_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .recalc_rate = ds3231_clk_32khz_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) static struct clk_init_data ds3231_clks_init[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) [DS3231_CLK_SQW] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .name = "ds3231_clk_sqw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .ops = &ds3231_clk_sqw_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) [DS3231_CLK_32KHZ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .name = "ds3231_clk_32khz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .ops = &ds3231_clk_32khz_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) static int ds3231_clks_register(struct ds1307 *ds1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) struct device_node *node = ds1307->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) struct clk_onecell_data *onecell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) onecell = devm_kzalloc(ds1307->dev, sizeof(*onecell), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) if (!onecell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) onecell->clk_num = ARRAY_SIZE(ds3231_clks_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) onecell->clks = devm_kcalloc(ds1307->dev, onecell->clk_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) sizeof(onecell->clks[0]), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) if (!onecell->clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) for (i = 0; i < ARRAY_SIZE(ds3231_clks_init); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) struct clk_init_data init = ds3231_clks_init[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) * Interrupt signal due to alarm conditions and square-wave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) * output share same pin, so don't initialize both.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (i == DS3231_CLK_SQW && test_bit(HAS_ALARM, &ds1307->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) /* optional override of the clockname */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) of_property_read_string_index(node, "clock-output-names", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) &init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) ds1307->clks[i].init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) onecell->clks[i] = devm_clk_register(ds1307->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) &ds1307->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) if (IS_ERR(onecell->clks[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) return PTR_ERR(onecell->clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) of_clk_add_provider(node, of_clk_src_onecell_get, onecell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) static void ds1307_clks_register(struct ds1307 *ds1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) if (ds1307->type != ds_3231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) ret = ds3231_clks_register(ds1307);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) dev_warn(ds1307->dev, "unable to register clock device %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) static void ds1307_clks_register(struct ds1307 *ds1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) #endif /* CONFIG_COMMON_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) #ifdef CONFIG_WATCHDOG_CORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) static const struct watchdog_info ds1388_wdt_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .identity = "DS1388 watchdog",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) static const struct watchdog_ops ds1388_wdt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .start = ds1388_wdt_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .stop = ds1388_wdt_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .ping = ds1388_wdt_ping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .set_timeout = ds1388_wdt_set_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) static void ds1307_wdt_register(struct ds1307 *ds1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) struct watchdog_device *wdt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) if (ds1307->type != ds_1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) wdt = devm_kzalloc(ds1307->dev, sizeof(*wdt), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if (!wdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) err = regmap_read(ds1307->regmap, DS1388_REG_FLAG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) if (!err && val & DS1388_BIT_WF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) wdt->bootstatus = WDIOF_CARDRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) wdt->info = &ds1388_wdt_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) wdt->ops = &ds1388_wdt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) wdt->timeout = 99;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) wdt->max_timeout = 99;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) wdt->min_timeout = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) watchdog_init_timeout(wdt, 0, ds1307->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) watchdog_set_drvdata(wdt, ds1307);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) devm_watchdog_register_device(ds1307->dev, wdt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) static void ds1307_wdt_register(struct ds1307 *ds1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) #endif /* CONFIG_WATCHDOG_CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) static const struct regmap_config regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) static int ds1307_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) struct ds1307 *ds1307;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) int err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) const struct chip_desc *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) bool want_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) bool ds1307_can_wakeup_device = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) unsigned char regs[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) struct ds1307_platform_data *pdata = dev_get_platdata(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) u8 trickle_charger_setup = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) ds1307 = devm_kzalloc(&client->dev, sizeof(struct ds1307), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) if (!ds1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) dev_set_drvdata(&client->dev, ds1307);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) ds1307->dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) ds1307->name = client->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) ds1307->regmap = devm_regmap_init_i2c(client, ®map_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) if (IS_ERR(ds1307->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) dev_err(ds1307->dev, "regmap allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) return PTR_ERR(ds1307->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) i2c_set_clientdata(client, ds1307);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) if (client->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) ds1307->type = (enum ds_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) of_device_get_match_data(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) chip = &chips[ds1307->type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) } else if (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) chip = &chips[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) ds1307->type = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) const struct acpi_device_id *acpi_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) acpi_id = acpi_match_device(ACPI_PTR(ds1307_acpi_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) ds1307->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) if (!acpi_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) chip = &chips[acpi_id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) ds1307->type = acpi_id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) want_irq = client->irq > 0 && chip->alarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) trickle_charger_setup = ds1307_trickle_init(ds1307, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) else if (pdata->trickle_charger_setup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) trickle_charger_setup = pdata->trickle_charger_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if (trickle_charger_setup && chip->trickle_charger_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) dev_dbg(ds1307->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) "writing trickle charger info 0x%x to 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) trickle_charger_setup, chip->trickle_charger_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) regmap_write(ds1307->regmap, chip->trickle_charger_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) trickle_charger_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) * For devices with no IRQ directly connected to the SoC, the RTC chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) * can be forced as a wakeup source by stating that explicitly in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) * the device's .dts file using the "wakeup-source" boolean property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) * If the "wakeup-source" property is set, don't request an IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) * This will guarantee the 'wakealarm' sysfs entry is available on the device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) * if supported by the RTC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) if (chip->alarm && of_property_read_bool(client->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) "wakeup-source"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) ds1307_can_wakeup_device = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) switch (ds1307->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) case ds_1337:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) case ds_1339:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) case ds_1341:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) case ds_3231:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) /* get registers that the "rtc" read below won't read... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) err = regmap_bulk_read(ds1307->regmap, DS1337_REG_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) regs, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) dev_dbg(ds1307->dev, "read error %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) /* oscillator off? turn it on, so clock can tick. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) if (regs[0] & DS1337_BIT_nEOSC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) regs[0] &= ~DS1337_BIT_nEOSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) * Using IRQ or defined as wakeup-source?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) * Disable the square wave and both alarms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) * For some variants, be sure alarms can trigger when we're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) * running on Vbackup (BBSQI/BBSQW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) if (want_irq || ds1307_can_wakeup_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) regs[0] |= DS1337_BIT_INTCN | chip->bbsqi_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) regs[0] &= ~(DS1337_BIT_A2IE | DS1337_BIT_A1IE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) regmap_write(ds1307->regmap, DS1337_REG_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) regs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) /* oscillator fault? clear flag, and warn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) if (regs[1] & DS1337_BIT_OSF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) regmap_write(ds1307->regmap, DS1337_REG_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) regs[1] & ~DS1337_BIT_OSF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) dev_warn(ds1307->dev, "SET TIME!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) case rx_8025:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) err = regmap_bulk_read(ds1307->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) RX8025_REG_CTRL1 << 4 | 0x08, regs, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) dev_dbg(ds1307->dev, "read error %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) /* oscillator off? turn it on, so clock can tick. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) if (!(regs[1] & RX8025_BIT_XST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) regs[1] |= RX8025_BIT_XST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) regmap_write(ds1307->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) RX8025_REG_CTRL2 << 4 | 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) regs[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) dev_warn(ds1307->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) "oscillator stop detected - SET TIME!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) if (regs[1] & RX8025_BIT_PON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) regs[1] &= ~RX8025_BIT_PON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) regmap_write(ds1307->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) RX8025_REG_CTRL2 << 4 | 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) regs[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) dev_warn(ds1307->dev, "power-on detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) if (regs[1] & RX8025_BIT_VDET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) regs[1] &= ~RX8025_BIT_VDET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) regmap_write(ds1307->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) RX8025_REG_CTRL2 << 4 | 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) regs[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) dev_warn(ds1307->dev, "voltage drop detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) /* make sure we are running in 24hour mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) if (!(regs[0] & RX8025_BIT_2412)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) u8 hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) /* switch to 24 hour mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) regmap_write(ds1307->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) RX8025_REG_CTRL1 << 4 | 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) regs[0] | RX8025_BIT_2412);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) err = regmap_bulk_read(ds1307->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) RX8025_REG_CTRL1 << 4 | 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) regs, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) dev_dbg(ds1307->dev, "read error %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) /* correct hour */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) hour = bcd2bin(regs[DS1307_REG_HOUR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) if (hour == 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) hour = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) hour += 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) regmap_write(ds1307->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) DS1307_REG_HOUR << 4 | 0x08, hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) case ds_1388:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) err = regmap_read(ds1307->regmap, DS1388_REG_CONTROL, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) dev_dbg(ds1307->dev, "read error %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) /* oscillator off? turn it on, so clock can tick. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) if (tmp & DS1388_BIT_nEOSC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) tmp &= ~DS1388_BIT_nEOSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) regmap_write(ds1307->regmap, DS1388_REG_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) /* read RTC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) err = regmap_bulk_read(ds1307->regmap, chip->offset, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) sizeof(regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) dev_dbg(ds1307->dev, "read error %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (ds1307->type == mcp794xx &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) !(regs[DS1307_REG_WDAY] & MCP794XX_BIT_VBATEN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) regmap_write(ds1307->regmap, DS1307_REG_WDAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) regs[DS1307_REG_WDAY] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) MCP794XX_BIT_VBATEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) tmp = regs[DS1307_REG_HOUR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) switch (ds1307->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) case ds_1340:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) case m41t0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) case m41t00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) case m41t11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) * NOTE: ignores century bits; fix before deploying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) * systems that will run through year 2100.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) case rx_8025:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) if (!(tmp & DS1307_BIT_12HR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) * Be sure we're in 24 hour mode. Multi-master systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) * take note...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) tmp = bcd2bin(tmp & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) if (tmp == 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if (regs[DS1307_REG_HOUR] & DS1307_BIT_PM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) tmp += 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) regmap_write(ds1307->regmap, chip->offset + DS1307_REG_HOUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) bin2bcd(tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) if (want_irq || ds1307_can_wakeup_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) device_set_wakeup_capable(ds1307->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) set_bit(HAS_ALARM, &ds1307->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) ds1307->rtc = devm_rtc_allocate_device(ds1307->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) if (IS_ERR(ds1307->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) return PTR_ERR(ds1307->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) if (ds1307_can_wakeup_device && !want_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) dev_info(ds1307->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) "'wakeup-source' is set, request for an IRQ is disabled!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) /* We cannot support UIE mode if we do not have an IRQ line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) ds1307->rtc->uie_unsupported = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) if (want_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) err = devm_request_threaded_irq(ds1307->dev, client->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) chip->irq_handler ?: ds1307_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) IRQF_SHARED | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) ds1307->name, ds1307);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) client->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) device_set_wakeup_capable(ds1307->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) clear_bit(HAS_ALARM, &ds1307->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) dev_err(ds1307->dev, "unable to request IRQ!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) dev_dbg(ds1307->dev, "got IRQ %d\n", client->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) ds1307->rtc->ops = chip->rtc_ops ?: &ds13xx_rtc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) err = ds1307_add_frequency_test(ds1307);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) err = rtc_register_device(ds1307->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) if (chip->nvram_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) struct nvmem_config nvmem_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) .name = "ds1307_nvram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) .word_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .size = chip->nvram_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .reg_read = ds1307_nvram_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .reg_write = ds1307_nvram_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .priv = ds1307,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) ds1307->rtc->nvram_old_abi = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) rtc_nvmem_register(ds1307->rtc, &nvmem_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) ds1307_hwmon_register(ds1307);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) ds1307_clks_register(ds1307);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) ds1307_wdt_register(ds1307);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) static struct i2c_driver ds1307_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .name = "rtc-ds1307",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) .of_match_table = of_match_ptr(ds1307_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .acpi_match_table = ACPI_PTR(ds1307_acpi_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .probe = ds1307_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .id_table = ds1307_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) module_i2c_driver(ds1307_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) MODULE_DESCRIPTION("RTC driver for DS1307 and similar chips");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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