^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * rtc-ds1305.c -- driver for DS1305 and DS1306 SPI RTC chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spi/ds1305.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Registers ... mask DS1305_WRITE into register address to write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * otherwise you're reading it. All non-bitmask values are BCD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DS1305_WRITE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* RTC date/time ... the main special cases are that we:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * - Need fancy "hours" encoding in 12hour mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * - Don't rely on the "day-of-week" field (or tm_wday)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * - Are a 21st-century clock (2000 <= year < 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DS1305_RTC_LEN 7 /* bytes for RTC regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DS1305_SEC 0x00 /* register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DS1305_MIN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DS1305_HOUR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) # define DS1305_HR_12 0x40 /* set == 12 hr mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) # define DS1305_HR_PM 0x20 /* set == PM (12hr mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DS1305_WDAY 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DS1305_MDAY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DS1305_MON 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DS1305_YEAR 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* The two alarms have only sec/min/hour/wday fields (ALM_LEN).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * DS1305_ALM_DISABLE disables a match field (some combos are bad).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * NOTE that since we don't use WDAY, we limit ourselves to alarms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * only one day into the future (vs potentially up to a week).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * NOTE ALSO that while we could generate once-a-second IRQs (UIE), we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * don't currently support them. We'd either need to do it only when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * no alarm is pending (not the standard model), or to use the second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * alarm (implying that this is a DS1305 not DS1306, *and* that either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * it's wired up a second IRQ we know, or that INTCN is set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DS1305_ALM_LEN 4 /* bytes for ALM regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DS1305_ALM_DISABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DS1305_ALM0(r) (0x07 + (r)) /* register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DS1305_ALM1(r) (0x0b + (r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* three control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DS1305_CONTROL_LEN 3 /* bytes of control regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DS1305_CONTROL 0x0f /* register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) # define DS1305_nEOSC 0x80 /* low enables oscillator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) # define DS1305_WP 0x40 /* write protect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) # define DS1305_INTCN 0x04 /* clear == only int0 used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) # define DS1306_1HZ 0x04 /* enable 1Hz output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) # define DS1305_AEI1 0x02 /* enable ALM1 IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) # define DS1305_AEI0 0x01 /* enable ALM0 IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DS1305_STATUS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* status has just AEIx bits, mirrored as IRQFx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DS1305_TRICKLE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* trickle bits are defined in <linux/spi/ds1305.h> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* a bunch of NVRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DS1305_NVRAM_LEN 96 /* bytes of NVRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DS1305_NVRAM 0x20 /* register addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct ds1305 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define FLAG_EXITING 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) bool hr12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u8 ctrl[DS1305_CONTROL_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Utilities ... tolerate 12-hour AM/PM notation in case of non-Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * software (like a bootloader) which may require it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static unsigned bcd2hour(u8 bcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (bcd & DS1305_HR_12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned hour = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) bcd &= ~DS1305_HR_12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (bcd & DS1305_HR_PM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) hour = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) bcd &= ~DS1305_HR_PM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) hour += bcd2bin(bcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return hour - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return bcd2bin(bcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static u8 hour2bcd(bool hr12, int hour)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (hr12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) hour++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (hour <= 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return DS1305_HR_12 | bin2bcd(hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) hour -= 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return DS1305_HR_12 | DS1305_HR_PM | bin2bcd(hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return bin2bcd(hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * Interface to RTC framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int ds1305_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct ds1305 *ds1305 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) long err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) buf[0] = DS1305_WRITE | DS1305_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) buf[1] = ds1305->ctrl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ds1305->ctrl[0] & DS1305_AEI0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) buf[1] |= DS1305_AEI0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!(buf[1] & DS1305_AEI0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) buf[1] &= ~DS1305_AEI0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) err = spi_write_then_read(ds1305->spi, buf, sizeof(buf), NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (err >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ds1305->ctrl[0] = buf[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * Get/set of date and time is pretty normal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int ds1305_get_time(struct device *dev, struct rtc_time *time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct ds1305 *ds1305 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u8 addr = DS1305_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u8 buf[DS1305_RTC_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Use write-then-read to get all the date/time registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * since dma from stack is nonportable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) status = spi_write_then_read(ds1305->spi, &addr, sizeof(addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dev_vdbg(dev, "%s: %3ph, %4ph\n", "read", &buf[0], &buf[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Decode the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) time->tm_sec = bcd2bin(buf[DS1305_SEC]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) time->tm_min = bcd2bin(buf[DS1305_MIN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) time->tm_hour = bcd2hour(buf[DS1305_HOUR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) time->tm_wday = buf[DS1305_WDAY] - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) time->tm_mday = bcd2bin(buf[DS1305_MDAY]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) time->tm_mon = bcd2bin(buf[DS1305_MON]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) time->tm_year = bcd2bin(buf[DS1305_YEAR]) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dev_vdbg(dev, "%s secs=%d, mins=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "read", time->tm_sec, time->tm_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) time->tm_hour, time->tm_mday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) time->tm_mon, time->tm_year, time->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int ds1305_set_time(struct device *dev, struct rtc_time *time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct ds1305 *ds1305 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u8 buf[1 + DS1305_RTC_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 *bp = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dev_vdbg(dev, "%s secs=%d, mins=%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "write", time->tm_sec, time->tm_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) time->tm_hour, time->tm_mday,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) time->tm_mon, time->tm_year, time->tm_wday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Write registers starting at the first time/date address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) *bp++ = DS1305_WRITE | DS1305_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) *bp++ = bin2bcd(time->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) *bp++ = bin2bcd(time->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *bp++ = hour2bcd(ds1305->hr12, time->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) *bp++ = (time->tm_wday < 7) ? (time->tm_wday + 1) : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) *bp++ = bin2bcd(time->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) *bp++ = bin2bcd(time->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *bp++ = bin2bcd(time->tm_year - 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev_dbg(dev, "%s: %3ph, %4ph\n", "write", &buf[1], &buf[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* use write-then-read since dma from stack is nonportable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return spi_write_then_read(ds1305->spi, buf, sizeof(buf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * Get/set of alarm is a bit funky:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * - First there's the inherent raciness of getting the (partitioned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * status of an alarm that could trigger while we're reading parts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * of that status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * - Second there's its limited range (we could increase it a bit by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * relying on WDAY), which means it will easily roll over.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * - Third there's the choice of two alarms and alarm signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * Here we use ALM0 and expect that nINT0 (open drain) is used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * that's the only real option for DS1306 runtime alarms, and is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * natural on DS1305.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * - Fourth, there's also ALM1, and a second interrupt signal:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * + On DS1305 ALM1 uses nINT1 (when INTCN=1) else nINT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * + On DS1306 ALM1 only uses INT1 (an active high pulse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * and it won't work when VCC1 is active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * So to be most general, we should probably set both alarms to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * same value, letting ALM1 be the wakeup event source on DS1306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * and handling several wiring options on DS1305.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * - Fifth, we support the polled mode (as well as possible; why not?)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * even when no interrupt line is wired to an IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int ds1305_get_alarm(struct device *dev, struct rtc_wkalrm *alm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct ds1305 *ds1305 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct spi_device *spi = ds1305->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u8 buf[DS1305_ALM_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Refresh control register cache BEFORE reading ALM0 registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * since reading alarm registers acks any pending IRQ. That
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * makes returning "pending" status a bit of a lie, but that bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * of EFI status is at best fragile anyway (given IRQ handlers).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) addr = DS1305_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) status = spi_write_then_read(spi, &addr, sizeof(addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ds1305->ctrl, sizeof(ds1305->ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) alm->enabled = !!(ds1305->ctrl[0] & DS1305_AEI0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) alm->pending = !!(ds1305->ctrl[1] & DS1305_AEI0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* get and check ALM0 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) addr = DS1305_ALM0(DS1305_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) status = spi_write_then_read(spi, &addr, sizeof(addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_vdbg(dev, "%s: %02x %02x %02x %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) "alm0 read", buf[DS1305_SEC], buf[DS1305_MIN],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) buf[DS1305_HOUR], buf[DS1305_WDAY]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if ((DS1305_ALM_DISABLE & buf[DS1305_SEC])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) || (DS1305_ALM_DISABLE & buf[DS1305_MIN])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) || (DS1305_ALM_DISABLE & buf[DS1305_HOUR]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Stuff these values into alm->time and let RTC framework code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * fill in the rest ... and also handle rollover to tomorrow when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * that's needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) alm->time.tm_sec = bcd2bin(buf[DS1305_SEC]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) alm->time.tm_min = bcd2bin(buf[DS1305_MIN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) alm->time.tm_hour = bcd2hour(buf[DS1305_HOUR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int ds1305_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct ds1305 *ds1305 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct spi_device *spi = ds1305->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned long now, later;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct rtc_time tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u8 buf[1 + DS1305_ALM_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* convert desired alarm to time_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) later = rtc_tm_to_time64(&alm->time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Read current time as time_t */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) status = ds1305_get_time(dev, &tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) now = rtc_tm_to_time64(&tm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* make sure alarm fires within the next 24 hours */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (later <= now)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if ((later - now) > 24 * 60 * 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return -EDOM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* disable alarm if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (ds1305->ctrl[0] & DS1305_AEI0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ds1305->ctrl[0] &= ~DS1305_AEI0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) buf[0] = DS1305_WRITE | DS1305_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) buf[1] = ds1305->ctrl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) status = spi_write_then_read(ds1305->spi, buf, 2, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* write alarm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) buf[0] = DS1305_WRITE | DS1305_ALM0(DS1305_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) buf[1 + DS1305_SEC] = bin2bcd(alm->time.tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) buf[1 + DS1305_MIN] = bin2bcd(alm->time.tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) buf[1 + DS1305_HOUR] = hour2bcd(ds1305->hr12, alm->time.tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) buf[1 + DS1305_WDAY] = DS1305_ALM_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dev_dbg(dev, "%s: %02x %02x %02x %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) "alm0 write", buf[1 + DS1305_SEC], buf[1 + DS1305_MIN],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) buf[1 + DS1305_HOUR], buf[1 + DS1305_WDAY]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* enable alarm if requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (alm->enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ds1305->ctrl[0] |= DS1305_AEI0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) buf[0] = DS1305_WRITE | DS1305_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) buf[1] = ds1305->ctrl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) status = spi_write_then_read(ds1305->spi, buf, 2, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int ds1305_proc(struct device *dev, struct seq_file *seq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct ds1305 *ds1305 = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) char *diodes = "no";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) char *resistors = "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* ctrl[2] is treated as read-only; no locking needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if ((ds1305->ctrl[2] & 0xf0) == DS1305_TRICKLE_MAGIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) switch (ds1305->ctrl[2] & 0x0c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case DS1305_TRICKLE_DS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) diodes = "2 diodes, ";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) case DS1305_TRICKLE_DS1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) diodes = "1 diode, ";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) switch (ds1305->ctrl[2] & 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) case DS1305_TRICKLE_2K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) resistors = "2k Ohm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case DS1305_TRICKLE_4K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) resistors = "4k Ohm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case DS1305_TRICKLE_8K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) resistors = "8k Ohm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) diodes = "no";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) seq_printf(seq, "trickle_charge\t: %s%s\n", diodes, resistors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define ds1305_proc NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static const struct rtc_class_ops ds1305_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .read_time = ds1305_get_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .set_time = ds1305_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .read_alarm = ds1305_get_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .set_alarm = ds1305_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .proc = ds1305_proc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .alarm_irq_enable = ds1305_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static void ds1305_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct ds1305 *ds1305 = container_of(work, struct ds1305, work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct mutex *lock = &ds1305->rtc->ops_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct spi_device *spi = ds1305->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u8 buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* lock to protect ds1305->ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) mutex_lock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Disable the IRQ, and clear its status ... for now, we "know"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * that if more than one alarm is active, they're in sync.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * Note that reading ALM data registers also clears IRQ status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ds1305->ctrl[0] &= ~(DS1305_AEI1 | DS1305_AEI0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ds1305->ctrl[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) buf[0] = DS1305_WRITE | DS1305_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) buf[1] = ds1305->ctrl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) buf[2] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) status = spi_write_then_read(spi, buf, sizeof(buf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dev_dbg(&spi->dev, "clear irq --> %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) mutex_unlock(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (!test_bit(FLAG_EXITING, &ds1305->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) enable_irq(spi->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) rtc_update_irq(ds1305->rtc, 1, RTC_AF | RTC_IRQF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * This "real" IRQ handler hands off to a workqueue mostly to allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * mutex locking for ds1305->ctrl ... unlike I2C, we could issue async
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * I/O requests in IRQ context (to clear the IRQ status).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static irqreturn_t ds1305_irq(int irq, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct ds1305 *ds1305 = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) disable_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) schedule_work(&ds1305->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * Interface for NVRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static void msg_init(struct spi_message *m, struct spi_transfer *x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u8 *addr, size_t count, char *tx, char *rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) spi_message_init(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) memset(x, 0, 2 * sizeof(*x));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) x->tx_buf = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) x->len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) spi_message_add_tail(x, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) x++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) x->tx_buf = tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) x->rx_buf = rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) x->len = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) spi_message_add_tail(x, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static int ds1305_nvram_read(void *priv, unsigned int off, void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct ds1305 *ds1305 = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct spi_device *spi = ds1305->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct spi_transfer x[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) addr = DS1305_NVRAM + off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) msg_init(&m, x, &addr, count, NULL, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return spi_sync(spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int ds1305_nvram_write(void *priv, unsigned int off, void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct ds1305 *ds1305 = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct spi_device *spi = ds1305->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct spi_transfer x[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) addr = (DS1305_WRITE | DS1305_NVRAM) + off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) msg_init(&m, x, &addr, count, buf, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return spi_sync(spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * Interface to SPI stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int ds1305_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct ds1305 *ds1305;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u8 addr, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct ds1305_platform_data *pdata = dev_get_platdata(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) bool write_ctrl = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct nvmem_config ds1305_nvmem_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .name = "ds1305_nvram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .word_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .size = DS1305_NVRAM_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .reg_read = ds1305_nvram_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .reg_write = ds1305_nvram_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* Sanity check board setup data. This may be hooked up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * in 3wire mode, but we don't care. Note that unless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * there's an inverter in place, this needs SPI_CS_HIGH!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if ((spi->bits_per_word && spi->bits_per_word != 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) || (spi->max_speed_hz > 2000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) || !(spi->mode & SPI_CPHA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* set up driver data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ds1305 = devm_kzalloc(&spi->dev, sizeof(*ds1305), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (!ds1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ds1305->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) spi_set_drvdata(spi, ds1305);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* read and cache control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) addr = DS1305_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) status = spi_write_then_read(spi, &addr, sizeof(addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ds1305->ctrl, sizeof(ds1305->ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) dev_dbg(&spi->dev, "can't %s, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) "read", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "read", ds1305->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* Sanity check register values ... partially compensating for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * fact that SPI has no device handshake. A pullup on MISO would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * make these tests fail; but not all systems will have one. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * some register is neither 0x00 nor 0xff, a chip is likely there.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if ((ds1305->ctrl[0] & 0x38) != 0 || (ds1305->ctrl[1] & 0xfc) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dev_dbg(&spi->dev, "RTC chip is not present\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (ds1305->ctrl[2] == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) dev_dbg(&spi->dev, "chip may not be present\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* enable writes if needed ... if we were paranoid it would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * make sense to enable them only when absolutely necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (ds1305->ctrl[0] & DS1305_WP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ds1305->ctrl[0] &= ~DS1305_WP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) buf[0] = DS1305_WRITE | DS1305_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) buf[1] = ds1305->ctrl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) dev_dbg(&spi->dev, "clear WP --> %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* on DS1305, maybe start oscillator; like most low power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * oscillators, it may take a second to stabilize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (ds1305->ctrl[0] & DS1305_nEOSC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ds1305->ctrl[0] &= ~DS1305_nEOSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) write_ctrl = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dev_warn(&spi->dev, "SET TIME!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* ack any pending IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (ds1305->ctrl[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ds1305->ctrl[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) write_ctrl = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* this may need one-time (re)init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* maybe enable trickle charge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (((ds1305->ctrl[2] & 0xf0) != DS1305_TRICKLE_MAGIC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ds1305->ctrl[2] = DS1305_TRICKLE_MAGIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) | pdata->trickle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) write_ctrl = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* on DS1306, configure 1 Hz signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (pdata->is_ds1306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (pdata->en_1hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (!(ds1305->ctrl[0] & DS1306_1HZ)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ds1305->ctrl[0] |= DS1306_1HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) write_ctrl = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (ds1305->ctrl[0] & DS1306_1HZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ds1305->ctrl[0] &= ~DS1306_1HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) write_ctrl = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (write_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) u8 buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) buf[0] = DS1305_WRITE | DS1305_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) buf[1] = ds1305->ctrl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) buf[2] = ds1305->ctrl[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) buf[3] = ds1305->ctrl[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) dev_dbg(&spi->dev, "can't %s, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) "write", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "write", ds1305->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* see if non-Linux software set up AM/PM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) addr = DS1305_HOUR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) status = spi_write_then_read(spi, &addr, sizeof(addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) &value, sizeof(value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dev_dbg(&spi->dev, "read HOUR --> %d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ds1305->hr12 = (DS1305_HR_12 & value) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (ds1305->hr12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) dev_dbg(&spi->dev, "AM/PM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* register RTC ... from here on, ds1305->ctrl needs locking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ds1305->rtc = devm_rtc_allocate_device(&spi->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (IS_ERR(ds1305->rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return PTR_ERR(ds1305->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ds1305->rtc->ops = &ds1305_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ds1305->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ds1305->rtc->range_max = RTC_TIMESTAMP_END_2099;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ds1305_nvmem_cfg.priv = ds1305;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ds1305->rtc->nvram_old_abi = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) status = rtc_register_device(ds1305->rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) rtc_nvmem_register(ds1305->rtc, &ds1305_nvmem_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* Maybe set up alarm IRQ; be ready to handle it triggering right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * away. NOTE that we don't share this. The signal is active low,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * and we can't ack it before a SPI message delay. We temporarily
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * disable the IRQ until it's acked, which lets us work with more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * IRQ trigger modes (not all IRQ controllers can do falling edge).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (spi->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) INIT_WORK(&ds1305->work, ds1305_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) status = devm_request_irq(&spi->dev, spi->irq, ds1305_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) 0, dev_name(&ds1305->rtc->dev), ds1305);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dev_err(&spi->dev, "request_irq %d --> %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) spi->irq, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) device_set_wakeup_capable(&spi->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static int ds1305_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct ds1305 *ds1305 = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* carefully shut down irq and workqueue, if present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (spi->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) set_bit(FLAG_EXITING, &ds1305->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) devm_free_irq(&spi->dev, spi->irq, ds1305);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) cancel_work_sync(&ds1305->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static struct spi_driver ds1305_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .driver.name = "rtc-ds1305",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .probe = ds1305_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .remove = ds1305_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* REVISIT add suspend/resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) module_spi_driver(ds1305_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) MODULE_DESCRIPTION("RTC driver for DS1305 and DS1306 chips");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) MODULE_ALIAS("spi:rtc-ds1305");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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