^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Dallas DS1302 RTC Support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2002 David McCullough
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2003 - 2007 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RTC_CMD_READ 0x81 /* Read command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RTC_CMD_WRITE 0x80 /* Write command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RTC_CMD_WRITE_ENABLE 0x00 /* Write enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RTC_CMD_WRITE_DISABLE 0x80 /* Write disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RTC_ADDR_RAM0 0x20 /* Address of RAM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RTC_ADDR_TCR 0x08 /* Address of trickle charge register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RTC_CLCK_BURST 0x1F /* Address of clock burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RTC_CLCK_LEN 0x08 /* Size of clock burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RTC_ADDR_CTRL 0x07 /* Address of control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RTC_ADDR_YEAR 0x06 /* Address of year register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RTC_ADDR_DAY 0x05 /* Address of day of week register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RTC_ADDR_MON 0x04 /* Address of month register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RTC_ADDR_DATE 0x03 /* Address of day of month register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RTC_ADDR_HOUR 0x02 /* Address of hour register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RTC_ADDR_MIN 0x01 /* Address of minute register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RTC_ADDR_SEC 0x00 /* Address of second register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int ds1302_rtc_set_time(struct device *dev, struct rtc_time *time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct spi_device *spi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 buf[1 + RTC_CLCK_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u8 *bp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Enable writing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) bp = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *bp++ = RTC_ADDR_CTRL << 1 | RTC_CMD_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *bp++ = RTC_CMD_WRITE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) status = spi_write_then_read(spi, buf, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Write registers starting at the first time/date address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) bp = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *bp++ = RTC_CLCK_BURST << 1 | RTC_CMD_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *bp++ = bin2bcd(time->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *bp++ = bin2bcd(time->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *bp++ = bin2bcd(time->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) *bp++ = bin2bcd(time->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *bp++ = bin2bcd(time->tm_mon + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *bp++ = time->tm_wday + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *bp++ = bin2bcd(time->tm_year % 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) *bp++ = RTC_CMD_WRITE_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* use write-then-read since dma from stack is nonportable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return spi_write_then_read(spi, buf, sizeof(buf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int ds1302_rtc_get_time(struct device *dev, struct rtc_time *time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct spi_device *spi = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u8 addr = RTC_CLCK_BURST << 1 | RTC_CMD_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 buf[RTC_CLCK_LEN - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Use write-then-read to get all the date/time registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * since dma from stack is nonportable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) status = spi_write_then_read(spi, &addr, sizeof(addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) buf, sizeof(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (status < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Decode the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) time->tm_sec = bcd2bin(buf[RTC_ADDR_SEC]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) time->tm_min = bcd2bin(buf[RTC_ADDR_MIN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) time->tm_hour = bcd2bin(buf[RTC_ADDR_HOUR]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) time->tm_wday = buf[RTC_ADDR_DAY] - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) time->tm_mday = bcd2bin(buf[RTC_ADDR_DATE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) time->tm_mon = bcd2bin(buf[RTC_ADDR_MON]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) time->tm_year = bcd2bin(buf[RTC_ADDR_YEAR]) + 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const struct rtc_class_ops ds1302_rtc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .read_time = ds1302_rtc_get_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .set_time = ds1302_rtc_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int ds1302_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 *bp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Sanity check board setup data. This may be hooked up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * in 3wire mode, but we don't care. Note that unless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * there's an inverter in place, this needs SPI_CS_HIGH!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (spi->bits_per_word && (spi->bits_per_word != 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dev_err(&spi->dev, "bad word length\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) } else if (spi->max_speed_hz > 2000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dev_err(&spi->dev, "speed is too high\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) } else if (spi->mode & SPI_CPHA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dev_err(&spi->dev, "bad mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) addr = RTC_ADDR_CTRL << 1 | RTC_CMD_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dev_err(&spi->dev, "control register read error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if ((buf[0] & ~RTC_CMD_WRITE_DISABLE) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) dev_err(&spi->dev, "control register read error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if ((buf[0] & ~RTC_CMD_WRITE_DISABLE) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dev_err(&spi->dev, "junk in control register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (buf[0] == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) bp = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *bp++ = RTC_ADDR_CTRL << 1 | RTC_CMD_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) *bp++ = RTC_CMD_WRITE_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) status = spi_write_then_read(spi, buf, 2, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dev_err(&spi->dev, "control register write error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) addr = RTC_ADDR_CTRL << 1 | RTC_CMD_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) status = spi_write_then_read(spi, &addr, sizeof(addr), buf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dev_err(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "error %d reading control register\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (buf[0] != RTC_CMD_WRITE_DISABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dev_err(&spi->dev, "failed to detect chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) spi_set_drvdata(spi, spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) rtc = devm_rtc_device_register(&spi->dev, "ds1302",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) &ds1302_rtc_ops, THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (IS_ERR(rtc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) status = PTR_ERR(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dev_err(&spi->dev, "error %d registering rtc\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int ds1302_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) spi_set_drvdata(spi, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const struct of_device_id ds1302_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { .compatible = "maxim,ds1302", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MODULE_DEVICE_TABLE(of, ds1302_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static struct spi_driver ds1302_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .driver.name = "rtc-ds1302",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .driver.of_match_table = of_match_ptr(ds1302_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .probe = ds1302_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .remove = ds1302_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) module_spi_driver(ds1302_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MODULE_DESCRIPTION("Dallas DS1302 RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MODULE_AUTHOR("Paul Mundt, David McCullough");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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