^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * DS1286 Real Time Clock interface for Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1998, 1999, 2000 Ralf Baechle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2008 Thomas Bogendoerfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on code written by Paul Gortmaker.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/rtc/ds1286.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct ds1286_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 __iomem *rtcregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static inline u8 ds1286_rtc_read(struct ds1286_priv *priv, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) return __raw_readl(&priv->rtcregs[reg]) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static inline void ds1286_rtc_write(struct ds1286_priv *priv, u8 data, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) __raw_writel(data, &priv->rtcregs[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int ds1286_alarm_irq_enable(struct device *dev, unsigned int enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct ds1286_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Allow or mask alarm interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) val = ds1286_rtc_read(priv, RTC_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) val &= ~RTC_TDM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) val |= RTC_TDM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ds1286_rtc_write(priv, val, RTC_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #ifdef CONFIG_RTC_INTF_DEV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int ds1286_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct ds1286_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) case RTC_WIE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Mask watchdog int. enab. bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) val = ds1286_rtc_read(priv, RTC_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) val |= RTC_WAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ds1286_rtc_write(priv, val, RTC_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) case RTC_WIE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Allow watchdog interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) val = ds1286_rtc_read(priv, RTC_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) val &= ~RTC_WAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ds1286_rtc_write(priv, val, RTC_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ds1286_ioctl NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int ds1286_proc(struct device *dev, struct seq_file *seq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct ds1286_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned char month, cmd, amode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) const char *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) month = ds1286_rtc_read(priv, RTC_MONTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) seq_printf(seq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "oscillator\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "square_wave\t: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) (month & RTC_EOSC) ? "disabled" : "enabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) (month & RTC_ESQW) ? "disabled" : "enabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) amode = ((ds1286_rtc_read(priv, RTC_MINUTES_ALARM) & 0x80) >> 5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ((ds1286_rtc_read(priv, RTC_HOURS_ALARM) & 0x80) >> 6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ((ds1286_rtc_read(priv, RTC_DAY_ALARM) & 0x80) >> 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) switch (amode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) s = "each minute";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) s = "minutes match";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) s = "hours and minutes match";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) s = "days, hours and minutes match";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) s = "invalid";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) seq_printf(seq, "alarm_mode\t: %s\n", s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) cmd = ds1286_rtc_read(priv, RTC_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) seq_printf(seq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) "alarm_enable\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "wdog_alarm\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "alarm_mask\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "wdog_alarm_mask\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "interrupt_mode\t: %s\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "INTB_mode\t: %s_active\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "interrupt_pins\t: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) (cmd & RTC_TDF) ? "yes" : "no",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) (cmd & RTC_WAF) ? "yes" : "no",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) (cmd & RTC_TDM) ? "disabled" : "enabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) (cmd & RTC_WAM) ? "disabled" : "enabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) (cmd & RTC_PU_LVL) ? "pulse" : "level",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) (cmd & RTC_IBH_LO) ? "low" : "high",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) (cmd & RTC_IPSW) ? "unswapped" : "swapped");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ds1286_proc NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int ds1286_read_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct ds1286_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned char save_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned long uip_watchdog = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * read RTC once any update in progress is done. The update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * can take just over 2ms. We wait 10 to 20ms. There is no need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * to poll-wait (up to 1s - eeccch) for the falling edge of RTC_UIP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * If you need to know *exactly* when a second has started, enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * periodic update complete interrupts, (via ioctl) and then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * immediately read /dev/rtc which will block until you get the IRQ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Once the read clears, read the RTC time (again via ioctl). Easy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (ds1286_rtc_read(priv, RTC_CMD) & RTC_TE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) while (time_before(jiffies, uip_watchdog + 2*HZ/100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * Only the values that we read from the RTC are set. We leave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * tm_wday, tm_yday and tm_isdst untouched. Even though the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * RTC has RTC_DAY_OF_WEEK, we ignore it, as it is only updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * by the RTC when initially set to a non-zero value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) save_control = ds1286_rtc_read(priv, RTC_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ds1286_rtc_write(priv, (save_control|RTC_TE), RTC_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) tm->tm_sec = ds1286_rtc_read(priv, RTC_SECONDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) tm->tm_min = ds1286_rtc_read(priv, RTC_MINUTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) tm->tm_hour = ds1286_rtc_read(priv, RTC_HOURS) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) tm->tm_mday = ds1286_rtc_read(priv, RTC_DATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) tm->tm_mon = ds1286_rtc_read(priv, RTC_MONTH) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) tm->tm_year = ds1286_rtc_read(priv, RTC_YEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ds1286_rtc_write(priv, save_control, RTC_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) tm->tm_sec = bcd2bin(tm->tm_sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) tm->tm_min = bcd2bin(tm->tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) tm->tm_hour = bcd2bin(tm->tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) tm->tm_mday = bcd2bin(tm->tm_mday);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) tm->tm_mon = bcd2bin(tm->tm_mon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) tm->tm_year = bcd2bin(tm->tm_year);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Account for differences between how the RTC uses the values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * and how they are defined in a struct rtc_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (tm->tm_year < 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) tm->tm_year += 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) tm->tm_year += 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (tm->tm_year < 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) tm->tm_year += 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) tm->tm_mon--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int ds1286_set_time(struct device *dev, struct rtc_time *tm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct ds1286_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned char mon, day, hrs, min, sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned char save_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned int yrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) yrs = tm->tm_year + 1900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) mon = tm->tm_mon + 1; /* tm_mon starts at zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) day = tm->tm_mday;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) hrs = tm->tm_hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) min = tm->tm_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) sec = tm->tm_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (yrs < 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) yrs -= 1940;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (yrs > 255) /* They are unsigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (yrs >= 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) yrs -= 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) sec = bin2bcd(sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) min = bin2bcd(min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) hrs = bin2bcd(hrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) day = bin2bcd(day);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) mon = bin2bcd(mon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) yrs = bin2bcd(yrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) save_control = ds1286_rtc_read(priv, RTC_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ds1286_rtc_write(priv, (save_control|RTC_TE), RTC_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ds1286_rtc_write(priv, yrs, RTC_YEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ds1286_rtc_write(priv, mon, RTC_MONTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ds1286_rtc_write(priv, day, RTC_DATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ds1286_rtc_write(priv, hrs, RTC_HOURS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ds1286_rtc_write(priv, min, RTC_MINUTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ds1286_rtc_write(priv, sec, RTC_SECONDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ds1286_rtc_write(priv, 0, RTC_HUNDREDTH_SECOND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ds1286_rtc_write(priv, save_control, RTC_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int ds1286_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct ds1286_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * Only the values that we read from the RTC are set. That
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * means only tm_wday, tm_hour, tm_min.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) alm->time.tm_min = ds1286_rtc_read(priv, RTC_MINUTES_ALARM) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) alm->time.tm_hour = ds1286_rtc_read(priv, RTC_HOURS_ALARM) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) alm->time.tm_wday = ds1286_rtc_read(priv, RTC_DAY_ALARM) & 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ds1286_rtc_read(priv, RTC_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) alm->time.tm_min = bcd2bin(alm->time.tm_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) alm->time.tm_hour = bcd2bin(alm->time.tm_hour);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) alm->time.tm_sec = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int ds1286_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct ds1286_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned char hrs, min, sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) hrs = alm->time.tm_hour;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) min = alm->time.tm_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) sec = alm->time.tm_sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (hrs >= 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) hrs = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (min >= 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) min = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (sec != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) min = bin2bcd(min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) hrs = bin2bcd(hrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) spin_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ds1286_rtc_write(priv, hrs, RTC_HOURS_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ds1286_rtc_write(priv, min, RTC_MINUTES_ALARM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) spin_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const struct rtc_class_ops ds1286_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .ioctl = ds1286_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .proc = ds1286_proc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .read_time = ds1286_read_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .set_time = ds1286_set_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .read_alarm = ds1286_read_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .set_alarm = ds1286_set_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .alarm_irq_enable = ds1286_alarm_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static int ds1286_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct rtc_device *rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct ds1286_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) priv = devm_kzalloc(&pdev->dev, sizeof(struct ds1286_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) priv->rtcregs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (IS_ERR(priv->rtcregs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return PTR_ERR(priv->rtcregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) spin_lock_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) rtc = devm_rtc_device_register(&pdev->dev, "ds1286", &ds1286_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (IS_ERR(rtc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return PTR_ERR(rtc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) priv->rtc = rtc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static struct platform_driver ds1286_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .name = "rtc-ds1286",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .probe = ds1286_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) module_platform_driver(ds1286_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MODULE_AUTHOR("Thomas Bogendoerfer <tsbogend@alpha.franken.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) MODULE_DESCRIPTION("DS1286 RTC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MODULE_ALIAS("platform:rtc-ds1286");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags